locking/barriers: introduce new memory barrier gmb()

CVE-2017-5753
CVE-2017-5715

In constrast to existing mb() and rmb() barriers,
gmb() barrier is arch-independent and can be used to
implement any type of memory barrier.
In x86 case, it is either lfence or mfence, based on
processor type. ARM and others can define it according
to their needs.
Suggested-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Elena Reshetova <elena.reshetova@intel.com>
Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
(cherry picked from commit 15cdd6b1b8bdf69f6318b64650b342c38cc58451)
Signed-off-by: Andy Whitcroft <apw@canonical.com>

arch/x86/include/asm/barrier.h

@@ -24,6 +24,9 @@
 #define wmb()	asm volatile("sfence" ::: "memory")
 #endif
 
+#define gmb() alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC, \
+				       "lfence", X86_FEATURE_LFENCE_RDTSC);
+
 #ifdef CONFIG_X86_PPRO_FENCE
 #define dma_rmb()	rmb()
 #else

include/asm-generic/barrier.h

@@ -42,6 +42,10 @@
 #define wmb()	mb()
 #endif
 
+#ifndef gmb
+#define gmb()	do { } while (0)
+#endif
+
 #ifndef dma_rmb
 #define dma_rmb()	rmb()
 #endif