drm/i915/gt: Temporarily disable CPU caching into DMA for MTL
FIXME: It is suspected that some Address Translation Service (ATS) issue on IOMMU is causing CAT errors to occur on some MTL workloads. Applying a write barrier to the ppgtt set entry functions appeared to have no effect, so we must temporarily use I915_MAP_WC in the map_pt_dma class of functions on MTL until a proper ATS solution is found. Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> CC: Chris Wilson <chris.p.wilson@linux.intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Acked-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231102175831.872763-1-jonathan.cavitt@intel.com
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