Commit 35610745 authored by Kalle Valo's avatar Kalle Valo

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git

ath.git patches for v5.20. Major changes:

ath11k:

* fix WCN9074 to work again

* revert rfkill support as it was causing problems
parents 42bbf810 5cc8cc44
......@@ -140,8 +140,53 @@ ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector)
return ab->pci.msi.irqs[vector];
}
static inline u32
ath11k_ahb_get_window_start_wcn6750(struct ath11k_base *ab, u32 offset)
{
u32 window_start = 0;
/* If offset lies within DP register range, use 1st window */
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
window_start = ATH11K_PCI_WINDOW_START;
/* If offset lies within CE register range, use 2nd window */
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
ATH11K_PCI_WINDOW_RANGE_MASK)
window_start = 2 * ATH11K_PCI_WINDOW_START;
return window_start;
}
static void
ath11k_ahb_window_write32_wcn6750(struct ath11k_base *ab, u32 offset, u32 value)
{
u32 window_start;
/* WCN6750 uses static window based register access*/
window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
static u32 ath11k_ahb_window_read32_wcn6750(struct ath11k_base *ab, u32 offset)
{
u32 window_start;
u32 val;
/* WCN6750 uses static window based register access */
window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
return val;
}
static const struct ath11k_pci_ops ath11k_ahb_pci_ops_wcn6750 = {
.wakeup = NULL,
.release = NULL,
.get_msi_irq = ath11k_ahb_get_msi_irq_wcn6750,
.window_write32 = ath11k_ahb_window_write32_wcn6750,
.window_read32 = ath11k_ahb_window_read32_wcn6750,
};
static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
......@@ -971,11 +1016,16 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
}
ab->hif.ops = hif_ops;
ab->pci.ops = pci_ops;
ab->pdev = pdev;
ab->hw_rev = hw_rev;
platform_set_drvdata(pdev, ab);
ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
if (ret) {
ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
goto err_core_free;
}
ret = ath11k_core_pre_init(ab);
if (ret)
goto err_core_free;
......
......@@ -54,9 +54,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 11,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
.svc_to_ce_map_len = 21,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.single_pdev_only = false,
.rxdma1_enable = true,
.num_rxmda_per_pdev = 1,
......@@ -107,8 +104,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = true,
.static_window_map = false,
.hybrid_bus_type = false,
.dp_window_idx = 0,
.ce_window_idx = 0,
.fixed_fw_mem = false,
.support_off_channel_tx = false,
},
......@@ -133,9 +128,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 11,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
.svc_to_ce_map_len = 19,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.single_pdev_only = false,
.rxdma1_enable = true,
.num_rxmda_per_pdev = 1,
......@@ -183,8 +175,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = true,
.static_window_map = false,
.hybrid_bus_type = false,
.dp_window_idx = 0,
.ce_window_idx = 0,
.fixed_fw_mem = false,
.support_off_channel_tx = false,
},
......@@ -209,9 +199,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
.svc_to_ce_map_len = 14,
.rfkill_pin = 48,
.rfkill_cfg = 0,
.rfkill_on_level = 1,
.single_pdev_only = true,
.rxdma1_enable = false,
.num_rxmda_per_pdev = 2,
......@@ -258,8 +245,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = false,
.static_window_map = false,
.hybrid_bus_type = false,
.dp_window_idx = 0,
.ce_window_idx = 0,
.fixed_fw_mem = false,
.support_off_channel_tx = true,
},
......@@ -284,9 +269,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
.svc_to_ce_map_len = 18,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.rxdma1_enable = true,
.num_rxmda_per_pdev = 1,
.rx_mac_buf_ring = false,
......@@ -333,8 +315,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = false,
.static_window_map = true,
.hybrid_bus_type = false,
.dp_window_idx = 3,
.ce_window_idx = 2,
.fixed_fw_mem = false,
.support_off_channel_tx = false,
},
......@@ -359,9 +339,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
.svc_to_ce_map_len = 14,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.single_pdev_only = true,
.rxdma1_enable = false,
.num_rxmda_per_pdev = 2,
......@@ -408,8 +385,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = false,
.static_window_map = false,
.hybrid_bus_type = false,
.dp_window_idx = 0,
.ce_window_idx = 0,
.fixed_fw_mem = false,
.support_off_channel_tx = true,
},
......@@ -434,9 +409,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
.svc_to_ce_map_len = 14,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.single_pdev_only = true,
.rxdma1_enable = false,
.num_rxmda_per_pdev = 2,
......@@ -482,8 +454,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = false,
.static_window_map = false,
.hybrid_bus_type = false,
.dp_window_idx = 0,
.ce_window_idx = 0,
.fixed_fw_mem = false,
.support_off_channel_tx = true,
},
......@@ -508,9 +478,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.target_ce_count = 9,
.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
.svc_to_ce_map_len = 14,
.rfkill_pin = 0,
.rfkill_cfg = 0,
.rfkill_on_level = 0,
.single_pdev_only = true,
.rxdma1_enable = false,
.num_rxmda_per_pdev = 1,
......@@ -556,8 +523,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
.fixed_mem_region = false,
.static_window_map = true,
.hybrid_bus_type = true,
.dp_window_idx = 1,
.ce_window_idx = 2,
.fixed_fw_mem = true,
.support_off_channel_tx = false,
},
......@@ -1402,27 +1367,6 @@ static int ath11k_core_start_firmware(struct ath11k_base *ab,
return ret;
}
static int ath11k_core_rfkill_config(struct ath11k_base *ab)
{
struct ath11k *ar;
int ret = 0, i;
if (!(ab->target_caps.sys_cap_info & WMI_SYS_CAP_INFO_RFKILL))
return 0;
for (i = 0; i < ab->num_radios; i++) {
ar = ab->pdevs[i].ar;
ret = ath11k_mac_rfkill_config(ar);
if (ret && ret != -EOPNOTSUPP) {
ath11k_warn(ab, "failed to configure rfkill: %d", ret);
return ret;
}
}
return ret;
}
int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
{
int ret;
......@@ -1475,13 +1419,6 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
goto err_core_stop;
}
ath11k_hif_irq_enable(ab);
ret = ath11k_core_rfkill_config(ab);
if (ret && ret != -EOPNOTSUPP) {
ath11k_err(ab, "failed to config rfkill: %d\n", ret);
goto err_core_stop;
}
mutex_unlock(&ab->core_lock);
return 0;
......@@ -1550,7 +1487,6 @@ void ath11k_core_halt(struct ath11k *ar)
cancel_delayed_work_sync(&ar->scan.timeout);
cancel_work_sync(&ar->regd_update_work);
cancel_work_sync(&ab->update_11d_work);
cancel_work_sync(&ab->rfkill_work);
rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
synchronize_rcu();
......@@ -1558,28 +1494,6 @@ void ath11k_core_halt(struct ath11k *ar)
idr_init(&ar->txmgmt_idr);
}
static void ath11k_rfkill_work(struct work_struct *work)
{
struct ath11k_base *ab = container_of(work, struct ath11k_base, rfkill_work);
struct ath11k *ar;
bool rfkill_radio_on;
int i;
spin_lock_bh(&ab->base_lock);
rfkill_radio_on = ab->rfkill_radio_on;
spin_unlock_bh(&ab->base_lock);
for (i = 0; i < ab->num_radios; i++) {
ar = ab->pdevs[i].ar;
if (!ar)
continue;
/* notify cfg80211 radio state change */
ath11k_mac_rfkill_enable_radio(ar, rfkill_radio_on);
wiphy_rfkill_set_hw_state(ar->hw->wiphy, !rfkill_radio_on);
}
}
static void ath11k_update_11d(struct work_struct *work)
{
struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
......@@ -1891,7 +1805,6 @@ struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
init_waitqueue_head(&ab->qmi.cold_boot_waitq);
INIT_WORK(&ab->restart_work, ath11k_core_restart);
INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
INIT_WORK(&ab->rfkill_work, ath11k_rfkill_work);
INIT_WORK(&ab->reset_work, ath11k_core_reset);
timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
init_completion(&ab->htc_suspend);
......
......@@ -929,10 +929,6 @@ struct ath11k_base {
struct ath11k_dbring_cap *db_caps;
u32 num_db_cap;
struct work_struct rfkill_work;
/* true means radio is on */
bool rfkill_radio_on;
/* To synchronize 11d scan vdev id */
struct mutex vdev_id_11d_lock;
......
......@@ -153,9 +153,6 @@ struct ath11k_hw_params {
u32 svc_to_ce_map_len;
bool single_pdev_only;
u32 rfkill_pin;
u32 rfkill_cfg;
u32 rfkill_on_level;
bool rxdma1_enable;
int num_rxmda_per_pdev;
......@@ -201,8 +198,6 @@ struct ath11k_hw_params {
bool fixed_mem_region;
bool static_window_map;
bool hybrid_bus_type;
u8 dp_window_idx;
u8 ce_window_idx;
bool fixed_fw_mem;
bool support_off_channel_tx;
};
......
......@@ -5611,63 +5611,6 @@ static int ath11k_mac_mgmt_tx(struct ath11k *ar, struct sk_buff *skb,
return 0;
}
int ath11k_mac_rfkill_config(struct ath11k *ar)
{
struct ath11k_base *ab = ar->ab;
u32 param;
int ret;
if (ab->hw_params.rfkill_pin == 0)
return -EOPNOTSUPP;
ath11k_dbg(ab, ATH11K_DBG_MAC,
"mac rfkill_pin %d rfkill_cfg %d rfkill_on_level %d",
ab->hw_params.rfkill_pin, ab->hw_params.rfkill_cfg,
ab->hw_params.rfkill_on_level);
param = FIELD_PREP(WMI_RFKILL_CFG_RADIO_LEVEL,
ab->hw_params.rfkill_on_level) |
FIELD_PREP(WMI_RFKILL_CFG_GPIO_PIN_NUM,
ab->hw_params.rfkill_pin) |
FIELD_PREP(WMI_RFKILL_CFG_PIN_AS_GPIO,
ab->hw_params.rfkill_cfg);
ret = ath11k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
param, ar->pdev->pdev_id);
if (ret) {
ath11k_warn(ab,
"failed to set rfkill config 0x%x: %d\n",
param, ret);
return ret;
}
return 0;
}
int ath11k_mac_rfkill_enable_radio(struct ath11k *ar, bool enable)
{
enum wmi_rfkill_enable_radio param;
int ret;
if (enable)
param = WMI_RFKILL_ENABLE_RADIO_ON;
else
param = WMI_RFKILL_ENABLE_RADIO_OFF;
ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac %d rfkill enable %d",
ar->pdev_idx, param);
ret = ath11k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_RFKILL_ENABLE,
param, ar->pdev->pdev_id);
if (ret) {
ath11k_warn(ar->ab, "failed to set rfkill enable param %d: %d\n",
param, ret);
return ret;
}
return 0;
}
static void ath11k_mac_op_tx(struct ieee80211_hw *hw,
struct ieee80211_tx_control *control,
struct sk_buff *skb)
......@@ -5922,7 +5865,6 @@ static void ath11k_mac_op_stop(struct ieee80211_hw *hw)
cancel_delayed_work_sync(&ar->scan.timeout);
cancel_work_sync(&ar->regd_update_work);
cancel_work_sync(&ar->ab->update_11d_work);
cancel_work_sync(&ar->ab->rfkill_work);
if (ar->state_11d == ATH11K_11D_PREPARING) {
ar->state_11d = ATH11K_11D_IDLE;
......
......@@ -148,8 +148,6 @@ u8 ath11k_mac_hw_rate_to_idx(const struct ieee80211_supported_band *sband,
void __ath11k_mac_scan_finish(struct ath11k *ar);
void ath11k_mac_scan_finish(struct ath11k *ar);
int ath11k_mac_rfkill_enable_radio(struct ath11k *ar, bool enable);
int ath11k_mac_rfkill_config(struct ath11k *ar);
struct ath11k_vif *ath11k_mac_get_arvif(struct ath11k *ar, u32 vdev_id);
struct ath11k_vif *ath11k_mac_get_arvif_by_vdev_id(struct ath11k_base *ab,
......
......@@ -50,6 +50,22 @@ static void ath11k_pci_bus_release(struct ath11k_base *ab)
mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
}
static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
{
if (!ab->hw_params.static_window_map)
return ATH11K_PCI_WINDOW_START;
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
/* if offset lies within DP register range, use 3rd window */
return 3 * ATH11K_PCI_WINDOW_START;
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
ATH11K_PCI_WINDOW_RANGE_MASK)
/* if offset lies within CE register range, use 2nd window */
return 2 * ATH11K_PCI_WINDOW_START;
else
return ATH11K_PCI_WINDOW_START;
}
static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
{
struct ath11k_base *ab = ab_pci->ab;
......@@ -70,26 +86,39 @@ static void
ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 window_start = ATH11K_PCI_WINDOW_START;
u32 window_start;
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
window_start = ath11k_pci_get_window_start(ab, offset);
if (window_start == ATH11K_PCI_WINDOW_START) {
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
} else {
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
}
static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
{
struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
u32 window_start = ATH11K_PCI_WINDOW_START;
u32 val;
u32 window_start, val;
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
window_start = ath11k_pci_get_window_start(ab, offset);
if (window_start == ATH11K_PCI_WINDOW_START) {
spin_lock_bh(&ab_pci->window_lock);
ath11k_pci_select_window(ab_pci, offset);
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
spin_unlock_bh(&ab_pci->window_lock);
} else {
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}
return val;
}
......@@ -110,6 +139,8 @@ static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
};
static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
.wakeup = NULL,
.release = NULL,
.get_msi_irq = ath11k_pci_get_msi_irq,
.window_write32 = ath11k_pci_window_write32,
.window_read32 = ath11k_pci_window_read32,
......@@ -697,6 +728,7 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
struct ath11k_base *ab;
struct ath11k_pci *ab_pci;
u32 soc_hw_version_major, soc_hw_version_minor, addr;
const struct ath11k_pci_ops *pci_ops;
int ret;
ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
......@@ -754,10 +786,10 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
goto err_pci_free_region;
}
ab->pci.ops = &ath11k_pci_ops_qca6390;
pci_ops = &ath11k_pci_ops_qca6390;
break;
case QCN9074_DEVICE_ID:
ab->pci.ops = &ath11k_pci_ops_qcn9074;
pci_ops = &ath11k_pci_ops_qcn9074;
ab->hw_rev = ATH11K_HW_QCN9074_HW10;
break;
case WCN6855_DEVICE_ID:
......@@ -787,7 +819,7 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
goto err_pci_free_region;
}
ab->pci.ops = &ath11k_pci_ops_qca6390;
pci_ops = &ath11k_pci_ops_qca6390;
break;
default:
dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
......@@ -796,6 +828,12 @@ static int ath11k_pci_probe(struct pci_dev *pdev,
goto err_pci_free_region;
}
ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
if (ret) {
ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
goto err_pci_free_region;
}
ret = ath11k_pcic_init_msi_config(ab);
if (ret) {
ath11k_err(ab, "failed to init msi config: %d\n", ret);
......
......@@ -140,23 +140,8 @@ int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
}
EXPORT_SYMBOL(ath11k_pcic_init_msi_config);
static inline u32 ath11k_pcic_get_window_start(struct ath11k_base *ab,
u32 offset)
{
u32 window_start = 0;
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
window_start = ab->hw_params.dp_window_idx * ATH11K_PCI_WINDOW_START;
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
ATH11K_PCI_WINDOW_RANGE_MASK)
window_start = ab->hw_params.ce_window_idx * ATH11K_PCI_WINDOW_START;
return window_start;
}
void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
{
u32 window_start;
int ret = 0;
/* for offset beyond BAR + 4K - 32, may
......@@ -166,15 +151,10 @@ void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value)
offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->wakeup)
ret = ab->pci.ops->wakeup(ab);
if (offset < ATH11K_PCI_WINDOW_START) {
if (offset < ATH11K_PCI_WINDOW_START)
iowrite32(value, ab->mem + offset);
} else if (ab->hw_params.static_window_map) {
window_start = ath11k_pcic_get_window_start(ab, offset);
iowrite32(value, ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
} else if (ab->pci.ops->window_write32) {
else
ab->pci.ops->window_write32(ab, offset, value);
}
if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->release &&
......@@ -185,9 +165,8 @@ EXPORT_SYMBOL(ath11k_pcic_write32);
u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
{
u32 val = 0;
u32 window_start;
int ret = 0;
u32 val;
/* for offset beyond BAR + 4K - 32, may
* need to wakeup the device to access.
......@@ -196,15 +175,10 @@ u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset)
offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->wakeup)
ret = ab->pci.ops->wakeup(ab);
if (offset < ATH11K_PCI_WINDOW_START) {
if (offset < ATH11K_PCI_WINDOW_START)
val = ioread32(ab->mem + offset);
} else if (ab->hw_params.static_window_map) {
window_start = ath11k_pcic_get_window_start(ab, offset);
val = ioread32(ab->mem + window_start +
(offset & ATH11K_PCI_WINDOW_RANGE_MASK));
} else if (ab->pci.ops->window_read32) {
else
val = ab->pci.ops->window_read32(ab, offset);
}
if (test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) &&
offset >= ATH11K_PCI_ACCESS_ALWAYS_OFF && ab->pci.ops->release &&
......@@ -516,11 +490,6 @@ static irqreturn_t ath11k_pcic_ext_interrupt_handler(int irq, void *arg)
static int
ath11k_pcic_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
{
if (!ab->pci.ops->get_msi_irq) {
WARN_ONCE(1, "get_msi_irq pci op not defined");
return -EOPNOTSUPP;
}
return ab->pci.ops->get_msi_irq(ab, vector);
}
......@@ -746,3 +715,19 @@ int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
return 0;
}
EXPORT_SYMBOL(ath11k_pcic_map_service_to_pipe);
int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
const struct ath11k_pci_ops *pci_ops)
{
if (!pci_ops)
return 0;
/* Return error if mandatory pci_ops callbacks are missing */
if (!pci_ops->get_msi_irq || !pci_ops->window_write32 ||
!pci_ops->window_read32)
return -EINVAL;
ab->pci.ops = pci_ops;
return 0;
}
EXPORT_SYMBOL(ath11k_pcic_register_pci_ops);
......@@ -43,4 +43,6 @@ int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab);
void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab);
int ath11k_pcic_init_msi_config(struct ath11k_base *ab);
int ath11k_pcic_register_pci_ops(struct ath11k_base *ab,
const struct ath11k_pci_ops *pci_ops);
#endif
......@@ -129,8 +129,6 @@ static const struct wmi_tlv_policy wmi_tlv_policies[] = {
= { .min_len = sizeof(struct wmi_peer_assoc_conf_event) },
[WMI_TAG_STATS_EVENT]
= { .min_len = sizeof(struct wmi_stats_event) },
[WMI_TAG_RFKILL_EVENT] = {
.min_len = sizeof(struct wmi_rfkill_state_change_ev) },
[WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT]
= { .min_len = sizeof(struct wmi_pdev_ctl_failsafe_chk_event) },
[WMI_TAG_HOST_SWFDA_EVENT] = {
......@@ -533,8 +531,6 @@ static int ath11k_pull_service_ready_tlv(struct ath11k_base *ab,
cap->default_dbs_hw_mode_index = ev->default_dbs_hw_mode_index;
cap->num_msdu_desc = ev->num_msdu_desc;
ath11k_dbg(ab, ATH11K_DBG_WMI, "wmi sys cap info 0x%x\n", cap->sys_cap_info);
return 0;
}
......@@ -7566,40 +7562,6 @@ ath11k_wmi_pdev_dfs_radar_detected_event(struct ath11k_base *ab, struct sk_buff
kfree(tb);
}
static void ath11k_rfkill_state_change_event(struct ath11k_base *ab,
struct sk_buff *skb)
{
const struct wmi_rfkill_state_change_ev *ev;
const void **tb;
int ret;
tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC);
if (IS_ERR(tb)) {
ret = PTR_ERR(tb);
ath11k_warn(ab, "failed to parse tlv: %d\n", ret);
return;
}
ev = tb[WMI_TAG_RFKILL_EVENT];
if (!ev) {
kfree(tb);
return;
}
ath11k_dbg(ab, ATH11K_DBG_MAC,
"wmi tlv rfkill state change gpio %d type %d radio_state %d\n",
ev->gpio_pin_num,
ev->int_type,
ev->radio_state);
spin_lock_bh(&ab->base_lock);
ab->rfkill_radio_on = (ev->radio_state == WMI_RFKILL_RADIO_STATE_ON);
spin_unlock_bh(&ab->base_lock);
queue_work(ab->workqueue, &ab->rfkill_work);
kfree(tb);
}
static void
ath11k_wmi_pdev_temperature_event(struct ath11k_base *ab,
struct sk_buff *skb)
......@@ -7995,9 +7957,6 @@ static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb)
case WMI_11D_NEW_COUNTRY_EVENTID:
ath11k_reg_11d_new_cc_event(ab, skb);
break;
case WMI_RFKILL_STATE_CHANGE_EVENTID:
ath11k_rfkill_state_change_event(ab, skb);
break;
case WMI_DIAG_EVENTID:
ath11k_wmi_diag_event(ab, skb);
break;
......
......@@ -5328,31 +5328,6 @@ struct target_resource_config {
u32 twt_ap_sta_count;
};
enum wmi_sys_cap_info_flags {
WMI_SYS_CAP_INFO_RXTX_LED = BIT(0),
WMI_SYS_CAP_INFO_RFKILL = BIT(1),
};
#define WMI_RFKILL_CFG_GPIO_PIN_NUM GENMASK(5, 0)
#define WMI_RFKILL_CFG_RADIO_LEVEL BIT(6)
#define WMI_RFKILL_CFG_PIN_AS_GPIO GENMASK(10, 7)
enum wmi_rfkill_enable_radio {
WMI_RFKILL_ENABLE_RADIO_ON = 0,
WMI_RFKILL_ENABLE_RADIO_OFF = 1,
};
enum wmi_rfkill_radio_state {
WMI_RFKILL_RADIO_STATE_OFF = 1,
WMI_RFKILL_RADIO_STATE_ON = 2,
};
struct wmi_rfkill_state_change_ev {
u32 gpio_pin_num;
u32 int_type;
u32 radio_state;
} __packed;
enum wmi_debug_log_param {
WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1,
WMI_DEBUG_LOG_PARAM_VDEV_ENABLE,
......
......@@ -5,6 +5,7 @@ wcn36xx-y += main.o \
txrx.o \
smd.o \
pmc.o \
debug.o
debug.o \
firmware.o
wcn36xx-$(CONFIG_NL80211_TESTMODE) += testmode.o
......@@ -21,6 +21,7 @@
#include "wcn36xx.h"
#include "debug.h"
#include "pmc.h"
#include "firmware.h"
#ifdef CONFIG_WCN36XX_DEBUGFS
......@@ -136,6 +137,42 @@ static const struct file_operations fops_wcn36xx_dump = {
.write = write_file_dump,
};
static ssize_t read_file_firmware_feature_caps(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos)
{
struct wcn36xx *wcn = file->private_data;
size_t len = 0, buf_len = 2048;
char *buf;
int i;
int ret;
buf = kzalloc(buf_len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
mutex_lock(&wcn->hal_mutex);
for (i = 0; i < MAX_FEATURE_SUPPORTED; i++) {
if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, i)) {
len += scnprintf(buf + len, buf_len - len, "%s\n",
wcn36xx_firmware_get_cap_name(i));
}
if (len >= buf_len)
break;
}
mutex_unlock(&wcn->hal_mutex);
ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
kfree(buf);
return ret;
}
static const struct file_operations fops_wcn36xx_firmware_feat_caps = {
.open = simple_open,
.read = read_file_firmware_feature_caps,
};
#define ADD_FILE(name, mode, fop, priv_data) \
do { \
struct dentry *d; \
......@@ -163,6 +200,8 @@ void wcn36xx_debugfs_init(struct wcn36xx *wcn)
ADD_FILE(bmps_switcher, 0600, &fops_wcn36xx_bmps, wcn);
ADD_FILE(dump, 0200, &fops_wcn36xx_dump, wcn);
ADD_FILE(firmware_feat_caps, 0200,
&fops_wcn36xx_firmware_feat_caps, wcn);
}
void wcn36xx_debugfs_exit(struct wcn36xx *wcn)
......
......@@ -31,6 +31,7 @@ struct wcn36xx_dfs_entry {
struct dentry *rootdir;
struct wcn36xx_dfs_file file_bmps_switcher;
struct wcn36xx_dfs_file file_dump;
struct wcn36xx_dfs_file file_firmware_feat_caps;
};
void wcn36xx_debugfs_init(struct wcn36xx *wcn);
......
// SPDX-License-Identifier: GPL-2.0-only
#include "wcn36xx.h"
#include "firmware.h"
#define DEFINE(s)[s] = #s
static const char * const wcn36xx_firmware_caps_names[] = {
DEFINE(MCC),
DEFINE(P2P),
DEFINE(DOT11AC),
DEFINE(SLM_SESSIONIZATION),
DEFINE(DOT11AC_OPMODE),
DEFINE(SAP32STA),
DEFINE(TDLS),
DEFINE(P2P_GO_NOA_DECOUPLE_INIT_SCAN),
DEFINE(WLANACTIVE_OFFLOAD),
DEFINE(BEACON_OFFLOAD),
DEFINE(SCAN_OFFLOAD),
DEFINE(ROAM_OFFLOAD),
DEFINE(BCN_MISS_OFFLOAD),
DEFINE(STA_POWERSAVE),
DEFINE(STA_ADVANCED_PWRSAVE),
DEFINE(AP_UAPSD),
DEFINE(AP_DFS),
DEFINE(BLOCKACK),
DEFINE(PHY_ERR),
DEFINE(BCN_FILTER),
DEFINE(RTT),
DEFINE(RATECTRL),
DEFINE(WOW),
DEFINE(WLAN_ROAM_SCAN_OFFLOAD),
DEFINE(SPECULATIVE_PS_POLL),
DEFINE(SCAN_SCH),
DEFINE(IBSS_HEARTBEAT_OFFLOAD),
DEFINE(WLAN_SCAN_OFFLOAD),
DEFINE(WLAN_PERIODIC_TX_PTRN),
DEFINE(ADVANCE_TDLS),
DEFINE(BATCH_SCAN),
DEFINE(FW_IN_TX_PATH),
DEFINE(EXTENDED_NSOFFLOAD_SLOT),
DEFINE(CH_SWITCH_V1),
DEFINE(HT40_OBSS_SCAN),
DEFINE(UPDATE_CHANNEL_LIST),
DEFINE(WLAN_MCADDR_FLT),
DEFINE(WLAN_CH144),
DEFINE(NAN),
DEFINE(TDLS_SCAN_COEXISTENCE),
DEFINE(LINK_LAYER_STATS_MEAS),
DEFINE(MU_MIMO),
DEFINE(EXTENDED_SCAN),
DEFINE(DYNAMIC_WMM_PS),
DEFINE(MAC_SPOOFED_SCAN),
DEFINE(BMU_ERROR_GENERIC_RECOVERY),
DEFINE(DISA),
DEFINE(FW_STATS),
DEFINE(WPS_PRBRSP_TMPL),
DEFINE(BCN_IE_FLT_DELTA),
DEFINE(TDLS_OFF_CHANNEL),
DEFINE(RTT3),
DEFINE(MGMT_FRAME_LOGGING),
DEFINE(ENHANCED_TXBD_COMPLETION),
DEFINE(LOGGING_ENHANCEMENT),
DEFINE(EXT_SCAN_ENHANCED),
DEFINE(MEMORY_DUMP_SUPPORTED),
DEFINE(PER_PKT_STATS_SUPPORTED),
DEFINE(EXT_LL_STAT),
DEFINE(WIFI_CONFIG),
DEFINE(ANTENNA_DIVERSITY_SELECTION),
};
#undef DEFINE
const char *wcn36xx_firmware_get_cap_name(enum wcn36xx_firmware_feat_caps x)
{
if (x >= ARRAY_SIZE(wcn36xx_firmware_caps_names))
return "UNKNOWN";
return wcn36xx_firmware_caps_names[x];
}
void wcn36xx_firmware_set_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
bitmap[arr_idx] |= (1 << bit_idx);
}
int wcn36xx_firmware_get_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return -EINVAL;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0;
}
void wcn36xx_firmware_clear_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
bitmap[arr_idx] &= ~(1 << bit_idx);
}
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _FIRMWARE_H_
#define _FIRMWARE_H_
/* Capability bitmap exchange definitions and macros starts */
enum wcn36xx_firmware_feat_caps {
MCC = 0,
P2P = 1,
DOT11AC = 2,
SLM_SESSIONIZATION = 3,
DOT11AC_OPMODE = 4,
SAP32STA = 5,
TDLS = 6,
P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
WLANACTIVE_OFFLOAD = 8,
BEACON_OFFLOAD = 9,
SCAN_OFFLOAD = 10,
ROAM_OFFLOAD = 11,
BCN_MISS_OFFLOAD = 12,
STA_POWERSAVE = 13,
STA_ADVANCED_PWRSAVE = 14,
AP_UAPSD = 15,
AP_DFS = 16,
BLOCKACK = 17,
PHY_ERR = 18,
BCN_FILTER = 19,
RTT = 20,
RATECTRL = 21,
WOW = 22,
WLAN_ROAM_SCAN_OFFLOAD = 23,
SPECULATIVE_PS_POLL = 24,
SCAN_SCH = 25,
IBSS_HEARTBEAT_OFFLOAD = 26,
WLAN_SCAN_OFFLOAD = 27,
WLAN_PERIODIC_TX_PTRN = 28,
ADVANCE_TDLS = 29,
BATCH_SCAN = 30,
FW_IN_TX_PATH = 31,
EXTENDED_NSOFFLOAD_SLOT = 32,
CH_SWITCH_V1 = 33,
HT40_OBSS_SCAN = 34,
UPDATE_CHANNEL_LIST = 35,
WLAN_MCADDR_FLT = 36,
WLAN_CH144 = 37,
NAN = 38,
TDLS_SCAN_COEXISTENCE = 39,
LINK_LAYER_STATS_MEAS = 40,
MU_MIMO = 41,
EXTENDED_SCAN = 42,
DYNAMIC_WMM_PS = 43,
MAC_SPOOFED_SCAN = 44,
BMU_ERROR_GENERIC_RECOVERY = 45,
DISA = 46,
FW_STATS = 47,
WPS_PRBRSP_TMPL = 48,
BCN_IE_FLT_DELTA = 49,
TDLS_OFF_CHANNEL = 51,
RTT3 = 52,
MGMT_FRAME_LOGGING = 53,
ENHANCED_TXBD_COMPLETION = 54,
LOGGING_ENHANCEMENT = 55,
EXT_SCAN_ENHANCED = 56,
MEMORY_DUMP_SUPPORTED = 57,
PER_PKT_STATS_SUPPORTED = 58,
EXT_LL_STAT = 60,
WIFI_CONFIG = 61,
ANTENNA_DIVERSITY_SELECTION = 62,
MAX_FEATURE_SUPPORTED = 128,
};
void wcn36xx_firmware_set_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap);
int wcn36xx_firmware_get_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap);
void wcn36xx_firmware_clear_feat_caps(u32 *bitmap,
enum wcn36xx_firmware_feat_caps cap);
const char *wcn36xx_firmware_get_cap_name(enum wcn36xx_firmware_feat_caps x);
#endif /* _FIRMWARE_H_ */
......@@ -4758,74 +4758,6 @@ struct wcn36xx_hal_set_power_params_resp {
u32 status;
} __packed;
/* Capability bitmap exchange definitions and macros starts */
enum place_holder_in_cap_bitmap {
MCC = 0,
P2P = 1,
DOT11AC = 2,
SLM_SESSIONIZATION = 3,
DOT11AC_OPMODE = 4,
SAP32STA = 5,
TDLS = 6,
P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
WLANACTIVE_OFFLOAD = 8,
BEACON_OFFLOAD = 9,
SCAN_OFFLOAD = 10,
ROAM_OFFLOAD = 11,
BCN_MISS_OFFLOAD = 12,
STA_POWERSAVE = 13,
STA_ADVANCED_PWRSAVE = 14,
AP_UAPSD = 15,
AP_DFS = 16,
BLOCKACK = 17,
PHY_ERR = 18,
BCN_FILTER = 19,
RTT = 20,
RATECTRL = 21,
WOW = 22,
WLAN_ROAM_SCAN_OFFLOAD = 23,
SPECULATIVE_PS_POLL = 24,
SCAN_SCH = 25,
IBSS_HEARTBEAT_OFFLOAD = 26,
WLAN_SCAN_OFFLOAD = 27,
WLAN_PERIODIC_TX_PTRN = 28,
ADVANCE_TDLS = 29,
BATCH_SCAN = 30,
FW_IN_TX_PATH = 31,
EXTENDED_NSOFFLOAD_SLOT = 32,
CH_SWITCH_V1 = 33,
HT40_OBSS_SCAN = 34,
UPDATE_CHANNEL_LIST = 35,
WLAN_MCADDR_FLT = 36,
WLAN_CH144 = 37,
NAN = 38,
TDLS_SCAN_COEXISTENCE = 39,
LINK_LAYER_STATS_MEAS = 40,
MU_MIMO = 41,
EXTENDED_SCAN = 42,
DYNAMIC_WMM_PS = 43,
MAC_SPOOFED_SCAN = 44,
BMU_ERROR_GENERIC_RECOVERY = 45,
DISA = 46,
FW_STATS = 47,
WPS_PRBRSP_TMPL = 48,
BCN_IE_FLT_DELTA = 49,
TDLS_OFF_CHANNEL = 51,
RTT3 = 52,
MGMT_FRAME_LOGGING = 53,
ENHANCED_TXBD_COMPLETION = 54,
LOGGING_ENHANCEMENT = 55,
EXT_SCAN_ENHANCED = 56,
MEMORY_DUMP_SUPPORTED = 57,
PER_PKT_STATS_SUPPORTED = 58,
EXT_LL_STAT = 60,
WIFI_CONFIG = 61,
ANTENNA_DIVERSITY_SELECTION = 62,
MAX_FEATURE_SUPPORTED = 128,
};
#define WCN36XX_HAL_CAPS_SIZE 4
struct wcn36xx_hal_feat_caps_msg {
......
......@@ -28,6 +28,7 @@
#include <net/ipv6.h>
#include "wcn36xx.h"
#include "testmode.h"
#include "firmware.h"
unsigned int wcn36xx_dbg_mask;
module_param_named(debug_mask, wcn36xx_dbg_mask, uint, 0644);
......@@ -192,88 +193,15 @@ static inline u8 get_sta_index(struct ieee80211_vif *vif,
sta_priv->sta_index;
}
#define DEFINE(s) [s] = #s
static const char * const wcn36xx_caps_names[] = {
DEFINE(MCC),
DEFINE(P2P),
DEFINE(DOT11AC),
DEFINE(SLM_SESSIONIZATION),
DEFINE(DOT11AC_OPMODE),
DEFINE(SAP32STA),
DEFINE(TDLS),
DEFINE(P2P_GO_NOA_DECOUPLE_INIT_SCAN),
DEFINE(WLANACTIVE_OFFLOAD),
DEFINE(BEACON_OFFLOAD),
DEFINE(SCAN_OFFLOAD),
DEFINE(ROAM_OFFLOAD),
DEFINE(BCN_MISS_OFFLOAD),
DEFINE(STA_POWERSAVE),
DEFINE(STA_ADVANCED_PWRSAVE),
DEFINE(AP_UAPSD),
DEFINE(AP_DFS),
DEFINE(BLOCKACK),
DEFINE(PHY_ERR),
DEFINE(BCN_FILTER),
DEFINE(RTT),
DEFINE(RATECTRL),
DEFINE(WOW),
DEFINE(WLAN_ROAM_SCAN_OFFLOAD),
DEFINE(SPECULATIVE_PS_POLL),
DEFINE(SCAN_SCH),
DEFINE(IBSS_HEARTBEAT_OFFLOAD),
DEFINE(WLAN_SCAN_OFFLOAD),
DEFINE(WLAN_PERIODIC_TX_PTRN),
DEFINE(ADVANCE_TDLS),
DEFINE(BATCH_SCAN),
DEFINE(FW_IN_TX_PATH),
DEFINE(EXTENDED_NSOFFLOAD_SLOT),
DEFINE(CH_SWITCH_V1),
DEFINE(HT40_OBSS_SCAN),
DEFINE(UPDATE_CHANNEL_LIST),
DEFINE(WLAN_MCADDR_FLT),
DEFINE(WLAN_CH144),
DEFINE(NAN),
DEFINE(TDLS_SCAN_COEXISTENCE),
DEFINE(LINK_LAYER_STATS_MEAS),
DEFINE(MU_MIMO),
DEFINE(EXTENDED_SCAN),
DEFINE(DYNAMIC_WMM_PS),
DEFINE(MAC_SPOOFED_SCAN),
DEFINE(BMU_ERROR_GENERIC_RECOVERY),
DEFINE(DISA),
DEFINE(FW_STATS),
DEFINE(WPS_PRBRSP_TMPL),
DEFINE(BCN_IE_FLT_DELTA),
DEFINE(TDLS_OFF_CHANNEL),
DEFINE(RTT3),
DEFINE(MGMT_FRAME_LOGGING),
DEFINE(ENHANCED_TXBD_COMPLETION),
DEFINE(LOGGING_ENHANCEMENT),
DEFINE(EXT_SCAN_ENHANCED),
DEFINE(MEMORY_DUMP_SUPPORTED),
DEFINE(PER_PKT_STATS_SUPPORTED),
DEFINE(EXT_LL_STAT),
DEFINE(WIFI_CONFIG),
DEFINE(ANTENNA_DIVERSITY_SELECTION),
};
#undef DEFINE
static const char *wcn36xx_get_cap_name(enum place_holder_in_cap_bitmap x)
{
if (x >= ARRAY_SIZE(wcn36xx_caps_names))
return "UNKNOWN";
return wcn36xx_caps_names[x];
}
static void wcn36xx_feat_caps_info(struct wcn36xx *wcn)
{
int i;
for (i = 0; i < MAX_FEATURE_SUPPORTED; i++) {
if (get_feat_caps(wcn->fw_feat_caps, i))
wcn36xx_dbg(WCN36XX_DBG_MAC, "FW Cap %s\n", wcn36xx_get_cap_name(i));
if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, i)) {
wcn36xx_dbg(WCN36XX_DBG_MAC, "FW Cap %s\n",
wcn36xx_firmware_get_cap_name(i));
}
}
}
......@@ -705,7 +633,7 @@ static int wcn36xx_hw_scan(struct ieee80211_hw *hw,
{
struct wcn36xx *wcn = hw->priv;
if (!get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) {
if (!wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) {
/* fallback to mac80211 software scan */
return 1;
}
......@@ -743,7 +671,7 @@ static void wcn36xx_cancel_hw_scan(struct ieee80211_hw *hw,
wcn->scan_aborted = true;
mutex_unlock(&wcn->scan_lock);
if (get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) {
if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) {
/* ieee80211_scan_completed will be called on FW scan
* indication */
wcn36xx_smd_stop_hw_scan(wcn);
......
......@@ -22,6 +22,7 @@
#include <linux/bitops.h>
#include <linux/rpmsg.h>
#include "smd.h"
#include "firmware.h"
struct wcn36xx_cfg_val {
u32 cfg_id;
......@@ -295,7 +296,7 @@ static void wcn36xx_smd_set_sta_vht_params(struct wcn36xx *wcn,
sta_params->vht_capable = sta->deflink.vht_cap.vht_supported;
sta_params->vht_ldpc_enabled =
is_cap_supported(caps, IEEE80211_VHT_CAP_RXLDPC);
if (get_feat_caps(wcn->fw_feat_caps, MU_MIMO)) {
if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, MU_MIMO)) {
sta_params->vht_tx_mu_beamformee_capable =
is_cap_supported(caps, IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
if (sta_params->vht_tx_mu_beamformee_capable)
......@@ -2431,49 +2432,6 @@ int wcn36xx_smd_dump_cmd_req(struct wcn36xx *wcn, u32 arg1, u32 arg2,
return ret;
}
void set_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
bitmap[arr_idx] |= (1 << bit_idx);
}
int get_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return -EINVAL;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0;
}
void clear_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap)
{
int arr_idx, bit_idx;
if (cap < 0 || cap > 127) {
wcn36xx_warn("error cap idx %d\n", cap);
return;
}
arr_idx = cap / 32;
bit_idx = cap % 32;
bitmap[arr_idx] &= ~(1 << bit_idx);
}
int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn)
{
struct wcn36xx_hal_feat_caps_msg msg_body, *rsp;
......@@ -2482,11 +2440,12 @@ int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn)
mutex_lock(&wcn->hal_mutex);
INIT_HAL_MSG(msg_body, WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ);
set_feat_caps(msg_body.feat_caps, STA_POWERSAVE);
wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, STA_POWERSAVE);
if (wcn->rf_id == RF_IRIS_WCN3680) {
set_feat_caps(msg_body.feat_caps, DOT11AC);
set_feat_caps(msg_body.feat_caps, WLAN_CH144);
set_feat_caps(msg_body.feat_caps, ANTENNA_DIVERSITY_SELECTION);
wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, DOT11AC);
wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, WLAN_CH144);
wcn36xx_firmware_set_feat_caps(msg_body.feat_caps,
ANTENNA_DIVERSITY_SELECTION);
}
PREPARE_HAL_BUF(wcn->hal_buf, msg_body);
......@@ -3300,7 +3259,7 @@ int wcn36xx_smd_add_beacon_filter(struct wcn36xx *wcn,
size_t payload_size;
int ret;
if (!get_feat_caps(wcn->fw_feat_caps, BCN_FILTER))
if (!wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, BCN_FILTER))
return -EOPNOTSUPP;
mutex_lock(&wcn->hal_mutex);
......
......@@ -125,9 +125,6 @@ int wcn36xx_smd_keep_alive_req(struct wcn36xx *wcn,
int wcn36xx_smd_dump_cmd_req(struct wcn36xx *wcn, u32 arg1, u32 arg2,
u32 arg3, u32 arg4, u32 arg5);
int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn);
void set_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap);
int get_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap);
void clear_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap);
int wcn36xx_smd_add_ba_session(struct wcn36xx *wcn,
struct ieee80211_sta *sta,
......
......@@ -1010,7 +1010,7 @@ static ssize_t wil_write_file_wmi(struct file *file, const char __user *buf,
void *cmd;
int cmdlen = len - sizeof(struct wmi_cmd_hdr);
u16 cmdid;
int rc, rc1;
int rc1;
if (cmdlen < 0 || *ppos != 0)
return -EINVAL;
......@@ -1027,7 +1027,7 @@ static ssize_t wil_write_file_wmi(struct file *file, const char __user *buf,
wil_info(wil, "0x%04x[%d] -> %d\n", cmdid, cmdlen, rc1);
return rc;
return len;
}
static const struct file_operations fops_wmi = {
......
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