Commit 365c83c3 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'spi-fix-v4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
 "A small collection of pretty much unremarkable driver specific fixes
  here plus the addition of a new device ID to spidev which requires no
  other code changes"

* tag 'spi-fix-v4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: imx: Fix small DMA transfers
  spi: zynq: missing break statement
  spi: SPI_ZYNQMP_GQSPI should depend on HAS_DMA
  spi: spidev: add compatible value for LTC2488
  spi: img-spfi: fix support for speeds up to 1/4th input clock
parents 5b7f00a5 0c38ec71
...@@ -612,7 +612,7 @@ config SPI_XTENSA_XTFPGA ...@@ -612,7 +612,7 @@ config SPI_XTENSA_XTFPGA
config SPI_ZYNQMP_GQSPI config SPI_ZYNQMP_GQSPI
tristate "Xilinx ZynqMP GQSPI controller" tristate "Xilinx ZynqMP GQSPI controller"
depends on SPI_MASTER depends on SPI_MASTER && HAS_DMA
help help
Enables Xilinx GQSPI controller driver for Zynq UltraScale+ MPSoC. Enables Xilinx GQSPI controller driver for Zynq UltraScale+ MPSoC.
......
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#define SPFI_CONTROL_SOFT_RESET BIT(11) #define SPFI_CONTROL_SOFT_RESET BIT(11)
#define SPFI_CONTROL_SEND_DMA BIT(10) #define SPFI_CONTROL_SEND_DMA BIT(10)
#define SPFI_CONTROL_GET_DMA BIT(9) #define SPFI_CONTROL_GET_DMA BIT(9)
#define SPFI_CONTROL_SE BIT(8)
#define SPFI_CONTROL_TMODE_SHIFT 5 #define SPFI_CONTROL_TMODE_SHIFT 5
#define SPFI_CONTROL_TMODE_MASK 0x7 #define SPFI_CONTROL_TMODE_MASK 0x7
#define SPFI_CONTROL_TMODE_SINGLE 0 #define SPFI_CONTROL_TMODE_SINGLE 0
...@@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi, ...@@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
else if (xfer->tx_nbits == SPI_NBITS_QUAD && else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
xfer->rx_nbits == SPI_NBITS_QUAD) xfer->rx_nbits == SPI_NBITS_QUAD)
val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT; val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
val |= SPFI_CONTROL_SE;
spfi_writel(spfi, val, SPFI_CONTROL); spfi_writel(spfi, val, SPFI_CONTROL);
} }
......
...@@ -201,8 +201,9 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, ...@@ -201,8 +201,9 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
{ {
struct spi_imx_data *spi_imx = spi_master_get_devdata(master); struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
if (spi_imx->dma_is_inited && (transfer->len > spi_imx->rx_wml) if (spi_imx->dma_is_inited
&& (transfer->len > spi_imx->tx_wml)) && transfer->len > spi_imx->rx_wml * sizeof(u32)
&& transfer->len > spi_imx->tx_wml * sizeof(u32))
return true; return true;
return false; return false;
} }
......
...@@ -214,6 +214,7 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, ...@@ -214,6 +214,7 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
case GQSPI_SELECT_FLASH_CS_BOTH: case GQSPI_SELECT_FLASH_CS_BOTH:
instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER | instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
GQSPI_GENFIFO_CS_UPPER; GQSPI_GENFIFO_CS_UPPER;
break;
case GQSPI_SELECT_FLASH_CS_UPPER: case GQSPI_SELECT_FLASH_CS_UPPER:
instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER; instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
break; break;
......
...@@ -693,6 +693,7 @@ static struct class *spidev_class; ...@@ -693,6 +693,7 @@ static struct class *spidev_class;
#ifdef CONFIG_OF #ifdef CONFIG_OF
static const struct of_device_id spidev_dt_ids[] = { static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "rohm,dh2228fv" }, { .compatible = "rohm,dh2228fv" },
{ .compatible = "lineartechnology,ltc2488" },
{}, {},
}; };
MODULE_DEVICE_TABLE(of, spidev_dt_ids); MODULE_DEVICE_TABLE(of, spidev_dt_ids);
......
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