Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Documentation/arm/IXP4xx

@@ -122,6 +122,15 @@ http://developer.intel.com/design/network/products/npfamily/ixdp425.htm
    also known as the Richfield board. It contains 4 PCI slots, 16MB
    of flash, two 10/100 ports and one ADSL port.
 
+Intel IXDPG425 Development Platform
+
+   This is basically and ADI Coyote board with a NEC EHCI controller
+   added. One issue with this board is that the mini-PCI slots only
+   have the 3.3v line connected, so you can't use a PCI to mini-PCI
+   adapter with an E100 card. So to NFS root you need to use either
+   the CSR or a WiFi card and a ramdisk that BOOTPs and then does
+   a pivot_root to NFS.
+
 Motorola PrPMC1100 Processor Mezanine Card
 http://www.fountainsys.com/datasheet/PrPMC1100.pdf
 
@@ -152,4 +161,4 @@ Robert E. Ranslam
 
 -------------------------------------------------------------------------
 
-Last Update: 5/13/2004
+Last Update: 11/16/2004

MAINTAINERS

@@ -287,6 +287,12 @@ P:	Dave Gilbert
 M:	linux@treblig.org
 S:	Maintained
 
+ARM/PLEB SUPPORT
+P:	Peter Chubb
+M:	pleb@gelato.unsw.edu.au
+W:	http://www.disy.cse.unsw.edu.au/Hardware/PLEB
+S:	Maintained
+
 ARM/PT DIGITAL BOARD PORT
 P:	Stefan Eletzhofer
 M:	stefan.eletzhofer@eletztrick.de

arch/arm/Kconfig

@@ -393,7 +393,7 @@ source "drivers/cpufreq/Kconfig"
 
 config CPU_FREQ_SA1100
 	bool
-	depends on CPU_FREQ && SA1100_LART
+	depends on CPU_FREQ && (SA1100_LART || SA1100_PLEB)
 	default y
 
 config CPU_FREQ_SA1110

arch/arm/mach-ixp2000/core.c

@@ -309,41 +309,6 @@ static struct irqchip ixp2000_pci_irq_chip = {
 	.unmask	= ixp2000_pci_irq_unmask
 };
 
-/*
- * Error interrupts. These are used extensively by the microengine drivers
- */
-static void ixp2000_err_irq_handler(unsigned int irq, struct irqdesc *desc,  struct pt_regs *regs)
-{
-	int i;
-	unsigned long status = *IXP2000_IRQ_ERR_STATUS;
-
-
-	for (i = 0; i <= 12; i++) {
-		if (status & (1 << i)) {
-			desc = irq_desc + IRQ_IXP2000_DRAM0_MIN_ERR + i;
-			desc->handle(IRQ_IXP2000_DRAM0_MIN_ERR + i, desc, regs);
-		}
-	}
-}
-
-static void ixp2000_err_irq_mask(unsigned int irq)
-{
-	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
-			(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
-}
-
-static void ixp2000_err_irq_unmask(unsigned int irq)
-{
-	ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
-			(1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
-}
-
-static struct irqchip ixp2000_err_irq_chip = {
-	.ack	= ixp2000_err_irq_mask,
-	.mask	= ixp2000_err_irq_mask,
-	.unmask	= ixp2000_err_irq_unmask
-};
-
 static void ixp2000_irq_mask(unsigned int irq)
 {
 	ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
@@ -387,7 +352,7 @@ void __init ixp2000_init_irq(void)
 	 * we mark the reserved IRQs as invalid. This makes
 	 * our mask/unmask code much simpler.
 	 */
-	for (irq = IRQ_IXP2000_SWI; irq <= IRQ_IXP2000_THDB3; irq++) {
+	for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
 		if((1 << irq) & IXP2000_VALID_IRQ_MASK) {
 			set_irq_chip(irq, &ixp2000_irq_chip);
 			set_irq_handler(irq, do_level_IRQ);
@@ -409,18 +374,11 @@ void __init ixp2000_init_irq(void)
 	/*
 	 * Enable PCI irq
 	 */
-	*(IXP2000_IRQ_ENABLE_SET) = (1 << IRQ_IXP2000_PCI);
+	ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
 	for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
 		set_irq_chip(irq, &ixp2000_pci_irq_chip);
 		set_irq_handler(irq, do_level_IRQ);
 		set_irq_flags(irq, IRQF_VALID);
 	}
-
-	for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
-		set_irq_chip(irq, &ixp2000_err_irq_chip);
-		set_irq_handler(irq, do_level_IRQ);
-		set_irq_flags(irq, IRQF_VALID);
-	}       
-	set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
 }
 

arch/arm/mach-ixp2000/ixdp2x01.c

@@ -51,12 +51,14 @@
  *************************************************************************/
 static void ixdp2x01_irq_mask(unsigned int irq)
 {
-	*IXDP2X01_INT_MASK_SET_REG = IXP2000_BOARD_IRQ_MASK(irq);
+	ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG,
+				IXP2000_BOARD_IRQ_MASK(irq));
 }
 
 static void ixdp2x01_irq_unmask(unsigned int irq)
 {
-	*IXDP2X01_INT_MASK_CLR_REG = IXP2000_BOARD_IRQ_MASK(irq);
+	ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
+				IXP2000_BOARD_IRQ_MASK(irq));
 }
 
 static u32 valid_irq_mask;
@@ -111,8 +113,8 @@ void __init ixdp2x01_init_irq(void)
 		valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
 
 	/* Mask all interrupts from CPLD, disable simulation */
-	*IXDP2X01_INT_MASK_SET_REG = 0xffffffff;
-	*IXDP2X01_INT_SIM_REG = 0;
+	ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
+	ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0);
 
 	for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
 		if (irq & valid_irq_mask) {
@@ -314,8 +316,8 @@ static struct flash_platform_data ixdp2x01_flash_platform_data = {
 
 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
 {
-	*IXDP2X01_CPLD_FLASH_REG = 
-		((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN);
+	ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
+		((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
 	return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
 }
 
@@ -340,14 +342,29 @@ static struct platform_device ixdp2x01_flash = {
 	.resource	= &ixdp2x01_flash_resource,
 };
 
+static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
+	.sda_pin	= IXDP2X01_GPIO_SDA,
+	.scl_pin	= IXDP2X01_GPIO_SCL,
+};
+
+static struct platform_device ixdp2x01_i2c_controller = {
+	.name		= "IXP2000-I2C",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &ixdp2x01_i2c_gpio_pins,
+	},
+	.num_resources	= 0
+};
+
 static struct platform_device *ixdp2x01_devices[] __initdata = {
-	&ixdp2x01_flash
+	&ixdp2x01_flash,
+	&ixdp2x01_i2c_controller
 };
 
 static void __init ixdp2x01_init_machine(void)
 {
-	*IXDP2X01_CPLD_FLASH_REG = 
-		(IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN);
+	ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
+		(IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
 	
 	ixdp2x01_flash_data.nr_banks =
 		((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);

arch/arm/mach-ixp2000/pci.c

@@ -148,13 +148,13 @@ int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_re
 	cli();
 	temp = *(IXP2000_PCI_CONTROL);
 	if (temp & ((1 << 8) | (1 << 5))) {
-		*(IXP2000_PCI_CONTROL) = temp;
+		ixp2000_reg_write(IXP2000_PCI_CONTROL, temp);
 	}
 
 	temp = *(IXP2000_PCI_CMDSTAT);
 	if (temp & (1 << 29)) {
 		while (temp & (1 << 29)) {	
-			*(IXP2000_PCI_CMDSTAT) = temp;
+			ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
 			temp = *(IXP2000_PCI_CMDSTAT);
 		}
 	}
@@ -178,13 +178,13 @@ clear_master_aborts(void)
 	cli();
 	temp = *(IXP2000_PCI_CONTROL);
 	if (temp & ((1 << 8) | (1 << 5))) {	
-		*(IXP2000_PCI_CONTROL) = temp;
+		ixp2000_reg_write(IXP2000_PCI_CONTROL, temp);
 	}
 
 	temp = *(IXP2000_PCI_CMDSTAT);
 	if (temp & (1 << 29)) {
 		while (temp & (1 << 29)) {
-			*(IXP2000_PCI_CMDSTAT) = temp;
+			ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
 			temp = *(IXP2000_PCI_CMDSTAT);
 		}
 	}

arch/arm/mach-ixp4xx/Kconfig

@@ -29,6 +29,13 @@ config ARCH_IXDP425
 	  IXDP425 Development Platform (Also known as Richfield).  
 	  For more information on this platform, see Documentation/arm/IXP4xx.
 
+config MACH_IXDPG425
+	bool "IXDPG425"
+	help
+	  Say 'Y' here if you want your kernel to support Intel's
+	  IXDPG425 Development Platform (Also known as Montajade).
+	  For more information on this platform, see Documentation/arm/IXP4xx.
+
 #
 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine 
 # number from the bootloader due to marketing monkeys, so we just enable it 

arch/arm/mach-ixp4xx/Makefile

@@ -5,6 +5,7 @@
 obj-y	+= common.o common-pci.o 
 
 obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-pci.o ixdp425-setup.o
+obj-$(CONFIG_MACH_IXDPG425)	+= ixdpg425-pci.o coyote-setup.o
 obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-pci.o coyote-setup.o
 obj-$(CONFIG_ARCH_PRPMC1100)	+= prpmc1100-pci.o prpmc1100-setup.o
 

arch/arm/mach-ixp4xx/coyote-setup.c

 /*
  * arch/arm/mach-ixp4xx/coyote-setup.c
  *
- * ADI Engineering Coyote board-setup 
+ * Board setup for ADI Engineering and IXDGP425 boards
  *
  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  *
@@ -30,7 +30,7 @@
 #endif
 
 /*
- * Only one serial port is connected on the Coyote.
+ * Only one serial port is connected on the Coyote & IXDPG425
  */
 static struct uart_port coyote_serial_port = {
 	.membase	= (char*)(IXP4XX_UART2_BASE_VIRT + REG_OFFSET),
@@ -47,6 +47,13 @@ static struct uart_port coyote_serial_port = {
 
 void __init coyote_map_io(void)
 {
+	if (machine_is_ixdpg425()) {
+		coyote_serial_port.membase =
+			(char*)(IXP4XX_UART1_BASE_VIRT + REG_OFFSET);
+		coyote_serial_port.mapbase = IXP4XX_UART1_BASE_PHYS;
+		coyote_serial_port.irq = IRQ_IXP4XX_UART1;
+	}
+
 	early_serial_setup(&coyote_serial_port);
 
 	ixp4xx_map_io();
@@ -79,10 +86,31 @@ static struct platform_device *coyote_devices[] __initdata = {
 
 static void __init coyote_init(void)
 {
+	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
+	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
+
 	platform_add_devices(&coyote_devices, ARRAY_SIZE(coyote_devices));
 }
 
-MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
+#ifdef CONFIG_ARCH_ADI_COYOTE
+MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
+        MAINTAINER("MontaVista Software, Inc.")
+        BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
+                IXP4XX_PERIPHERAL_BASE_VIRT)
+        MAPIO(coyote_map_io)
+        INITIRQ(ixp4xx_init_irq)
+	.timer		= &ixp4xx_timer,
+        BOOT_PARAMS(0x0100)
+	INIT_MACHINE(coyote_init)
+MACHINE_END
+#endif
+
+/*
+ * IXDPG425 is identical to Coyote except for which serial port
+ * is connected.
+ */
+#ifdef CONFIG_MACH_IXDPG425
+MACHINE_START(IXDPG425, "Intel IXDPG425")
         MAINTAINER("MontaVista Software, Inc.")
         BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
                 IXP4XX_PERIPHERAL_BASE_VIRT)
@@ -92,4 +120,5 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
         BOOT_PARAMS(0x0100)
 	INIT_MACHINE(coyote_init)
 MACHINE_END
+#endif
 

arch/arm/mach-ixp4xx/ixdpg425-pci.c

+/*
+ * arch/arch/mach-ixp4xx/ixdpg425-pci.c
+ *
+ * PCI setup routines for Intel IXDPG425 Platform
+ *
+ * Copyright (C) 2004 MontaVista Softwrae, Inc.
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+
+#include <asm/mach/pci.h>
+
+extern void ixp4xx_pci_preinit(void);
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+void __init ixdpg425_pci_preinit(void)
+{
+	gpio_line_config(6, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+	gpio_line_config(7, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+
+	gpio_line_isr_clear(6);
+	gpio_line_isr_clear(7);
+
+	ixp4xx_pci_preinit();
+}
+
+static int __init ixdpg425_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	if (slot == 12 || slot == 13)
+		return IRQ_IXP4XX_GPIO7;
+	else if (slot == 14)
+		return IRQ_IXP4XX_GPIO6;
+	else return -1;
+}
+
+struct hw_pci ixdpg425_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit =        ixdpg425_pci_preinit,
+	.swizzle =        pci_std_swizzle,
+	.setup =          ixp4xx_setup,
+	.scan =           ixp4xx_scan_bus,
+	.map_irq =        ixdpg425_map_irq,
+};
+
+int __init ixdpg425_pci_init(void)
+{
+	if (machine_is_ixdpg425())
+		pci_common_init(&ixdpg425_pci);
+	return 0;
+}
+
+subsys_initcall(ixdpg425_pci_init);

arch/arm/mach-sa1100/Kconfig

@@ -109,6 +109,14 @@ config SA1100_LART
 	  (also known as the LART).  See <http://www.lart.tudelft.nl/> for
 	  information on the LART.
 
+config SA1100_PLEB
+	bool "PLEB"
+	help
+	  Say Y here if you are using version 1 of the Portable Linux
+	  Embedded Board (also known as PLEB).
+	  See <http://www.disy.cse.unsw.edu.au/Hardware/PLEB/>
+	  for more information.
+
 config SA1100_SHANNON
 	bool "Shannon"
 	help

arch/arm/mach-sa1100/Makefile

@@ -35,6 +35,8 @@ obj-$(CONFIG_SA1100_JORNADA720)		+= jornada720.o
 obj-$(CONFIG_SA1100_LART)		+= lart.o
 led-$(CONFIG_SA1100_LART)		+= leds-lart.o
 
+obj-$(CONFIG_SA1100_PLEB)		+= pleb.o
+
 obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
 
 obj-$(CONFIG_SA1100_SIMPAD)		+= simpad.o

arch/arm/mach-sa1100/pleb.c

+/*
+ * linux/arch/arm/mach-sa1100/pleb.c
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <linux/mtd/partitions.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/serial_sa1100.h>
+#include <asm/arch/irqs.h>
+
+#include "generic.h"
+
+
+/*
+ * Ethernet IRQ mappings
+ */
+
+#define PLEB_ETH0_P		(0x20000300)	/* Ethernet 0 in PCMCIA0 IO */
+#define PLEB_ETH0_V		(0xf6000300)
+
+#define GPIO_ETH0_IRQ		GPIO_GPIO(21)
+#define GPIO_ETH0_EN		GPIO_GPIO(26)
+
+#define IRQ_GPIO_ETH0_IRQ	IRQ_GPIO21
+
+static struct resource smc91x_resources[] = {
+	[0] = {
+		.start	=  PLEB_ETH0_P,
+		.end	=  PLEB_ETH0_P | 0x03ffffff,
+		.flags	= IORESOURCE_MEM,
+	},
+#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
+	[1] = {
+		.start	= IRQ_GPIO_ETH0_IRQ,
+		.end	= IRQ_GPIO_ETH0_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+#endif
+};
+
+
+static struct platform_device smc91x_device = {
+	.name		= "smc91x",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(smc91x_resources),
+	.resource	= smc91x_resources,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&smc91x_device,
+};
+
+
+/*
+ * Pleb's memory map
+ * has flash memory (typically 4 or 8 meg) selected by
+ * the two SA1100 lowest chip select outputs.
+ */
+static struct resource pleb_flash_resources[] = {
+	[0] = {
+		.start = SA1100_CS0_PHYS,
+		.end   = SA1100_CS0_PHYS + SZ_8M - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = SA1100_CS1_PHYS,
+		.end   = SA1100_CS1_PHYS + SZ_8M - 1,
+		.flags = IORESOURCE_MEM,
+	}
+};
+
+
+static struct mtd_partition pleb_partitions[] = {
+	{
+		.name		= "blob",
+		.offset 	= 0,
+		.size		= 0x00020000,
+	}, {
+		.name		= "kernel",
+		.offset 	= MTDPART_OFS_APPEND,
+		.size		= 0x000e0000,
+	}, {
+		.name		= "rootfs",
+		.offset 	= MTDPART_OFS_APPEND,
+		.size		= 0x00300000,
+	}
+};
+
+
+static struct flash_platform_data pleb_flash_data = {
+	.map_name = "cfi_probe",
+	.parts = pleb_partitions,
+	.nr_parts = ARRAY_SIZE(pleb_partitions),
+};
+
+
+static void __init pleb_init(void)
+{
+	sa11x0_set_flash_data(&pleb_flash_data, pleb_flash_resources,
+			      ARRAY_SIZE(pleb_flash_resources));
+
+
+	platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+
+static void __init pleb_map_io(void)
+{
+	sa1100_map_io();
+
+	sa1100_register_uart(0, 3);
+        sa1100_register_uart(1, 1);
+
+        GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
+        GPDR |= GPIO_UART_TXD;
+        GPDR &= ~GPIO_UART_RXD;
+        PPAR |= PPAR_UPR;
+
+	/*
+	 * Fix expansion memory timing for network card
+	 */
+	MECR = ((2<<10) | (2<<5) | (2<<0));
+
+	/*
+	 * Enable the SMC ethernet controller
+	 */
+	GPDR |= GPIO_ETH0_EN;	/* set to output */
+	GPCR  = GPIO_ETH0_EN;	/* clear MCLK (enable smc) */
+
+	GPDR &= ~GPIO_ETH0_IRQ;
+
+	set_irq_type(GPIO_ETH0_IRQ, IRQT_FALLING);
+}
+
+MACHINE_START(PLEB, "PLEB")
+	BOOT_MEM(0xc0000000, 0x80000000, 0xf8000000)
+	MAPIO(pleb_map_io)
+	INITIRQ(sa1100_init_irq)
+	.timer		= &sa1100_timer,
+	.init_machine   = pleb_init,
+MACHINE_END

drivers/net/smc91x.h

@@ -92,6 +92,25 @@
 	} while (0)
 #define set_irq_type(irq, type)
 
+#elif defined(CONFIG_SA1100_PLEB)
+/* We can only do 16-bit reads and writes in the static memory space. */
+#define SMC_CAN_USE_8BIT	1
+#define SMC_CAN_USE_16BIT	1
+#define SMC_CAN_USE_32BIT	0
+#define SMC_IO_SHIFT		0
+#define SMC_NOWAIT		1
+
+#define SMC_inb(a, r)		inb((a) + (r))
+#define SMC_insb(a, r, p, l)	insb((a) + (r), p, (l))
+#define SMC_inw(a, r)		inw((a) + (r))
+#define SMC_insw(a, r, p, l)	insw((a) + (r), p, l)
+#define SMC_outb(v, a, r)	outb(v, (a) + (r))
+#define SMC_outsb(a, r, p, l)	outsb((a) + (r), p, (l))
+#define SMC_outw(v, a, r)	outw(v, (a) + (r))
+#define SMC_outsw(a, r, p, l)	outsw((a) + (r), p, l)
+
+#define set_irq_type(irq, type) do {} while (0)
+
 #elif defined(CONFIG_SA1100_ASSABET)
 
 #include <asm/arch/neponset.h>

include/asm-arm/arch-ixp2000/irqs.h

@@ -28,7 +28,7 @@
  * shift operation instead of having to map the IRQ number to
  * a HW IRQ number.
  */
-#define	IRQ_IXP2000_SWI			0 /* soft interrupt */
+#define	IRQ_IXP2000_SOFT_INT		0 /* soft interrupt */
 #define	IRQ_IXP2000_ERRSUM		1 /* OR of all bits in ErrorStatus reg*/
 #define	IRQ_IXP2000_UART		2
 #define	IRQ_IXP2000_GPIO		3
@@ -67,22 +67,7 @@
 #define IRQ_IXP2000_PCIA		40
 #define IRQ_IXP2000_PCIB		41
 
-/* Int sources from IRQ_ERROR_STATUS */
-#define IRQ_IXP2000_DRAM0_MIN_ERR	42
-#define IRQ_IXP2000_DRAM0_MAJ_ERR	43
-#define IRQ_IXP2000_DRAM1_MIN_ERR	44
-#define IRQ_IXP2000_DRAM1_MAJ_ERR	45
-#define IRQ_IXP2000_DRAM2_MIN_ERR	46
-#define IRQ_IXP2000_DRAM2_MAJ_ERR	47
-#define IRQ_IXP2000_SRAM0_ERR		48
-#define IRQ_IXP2000_SRAM1_ERR		49
-#define IRQ_IXP2000_SRAM2_ERR           50
-#define IRQ_IXP2000_SRAM3_ERR		51
-#define IRQ_IXP2000_MEDIA_ERR		52
-#define IRQ_IXP2000_PCI_ERR		53
-#define IRQ_IXP2000_SP_INT		54
-
-#define NR_IXP2000_IRQS                 55
+#define NR_IXP2000_IRQS                 42
 
 #define	IXP2000_BOARD_IRQ(x)		(NR_IXP2000_IRQS + (x))
 

include/asm-arm/arch-ixp2000/ixdp2x01.h

@@ -50,4 +50,8 @@
 
 #define	IXDP2X01_UART_CLK		1843200
 
+#define	IXDP2X01_GPIO_I2C_ENABLE	0x02
+#define	IXDP2X01_GPIO_SCL		0x07
+#define	IXDP2X01_GPIO_SDA		0x06
+
 #endif /* __IXDP2x01_H__ */

include/asm-arm/arch-s3c2410/timex.h

 /* linux/include/asm-arm/arch-s3c2410/timex.h
  *
- * (c) 2003 Simtec Electronics
+ * (c) 2003,2004 Simtec Electronics
  *  Ben Dooks <ben@simtec.co.uk>
  *
  * S3C2410 - time parameters
@@ -12,6 +12,7 @@
  * Changelog:
  *  02-Sep-2003 BJD  Created file
  *  05-Jan-2004 BJD  Updated for Linux 2.6.0
+ *  22-Nov-2004 BJD  Fixed CLOCK_TICK_RATE
 */
 
 #ifndef __ASM_ARCH_TIMEX_H
@@ -26,8 +27,8 @@ extern int s3c2410_clock_tick_rate;
 #define CLOCK_TICK_RATE (s3c2410_clock_tick_rate)
 #endif
 
-/* currently, the BAST uses 24MHz as a base clock rate */
-#define CLOCK_TICK_RATE 24000000
+/* currently, the BAST uses 12MHz as a base clock rate */
+#define CLOCK_TICK_RATE 12000000
 
 
 #endif /* __ASM_ARCH_TIMEX_H */