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Commit 39a71db1 authored by Yuantian Tang's avatar Yuantian Tang Committed by Shawn Guo
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arm64: dts: ls208xa: add cpu idle support 

ls208xa supports another cpu idle state which is pw20 which saves
more power when cpu is idle.
It was implemented through psci firmware.
Signed-off-by: default avatarTang Yuantian <andy.tang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 5334e1a2
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Showing with 39 additions and 0 deletions
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file @ 39a71db1
...@@ -53,6 +53,7 @@ cpu0: cpu@0 { ...@@ -53,6 +53,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0>; reg = <0x0>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -62,6 +63,7 @@ cpu1: cpu@1 { ...@@ -62,6 +63,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x1>; reg = <0x1>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
}; };
...@@ -70,6 +72,7 @@ cpu2: cpu@100 { ...@@ -70,6 +72,7 @@ cpu2: cpu@100 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x100>; reg = <0x100>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -79,6 +82,7 @@ cpu3: cpu@101 { ...@@ -79,6 +82,7 @@ cpu3: cpu@101 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x101>; reg = <0x101>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
}; };
...@@ -87,6 +91,7 @@ cpu4: cpu@200 { ...@@ -87,6 +91,7 @@ cpu4: cpu@200 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x200>; reg = <0x200>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -96,6 +101,7 @@ cpu5: cpu@201 { ...@@ -96,6 +101,7 @@ cpu5: cpu@201 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x201>; reg = <0x201>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
}; };
...@@ -105,6 +111,7 @@ cpu6: cpu@300 { ...@@ -105,6 +111,7 @@ cpu6: cpu@300 {
reg = <0x300>; reg = <0x300>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -113,6 +120,7 @@ cpu7: cpu@301 { ...@@ -113,6 +120,7 @@ cpu7: cpu@301 {
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x301>; reg = <0x301>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
}; };
...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { ...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 { cluster3_l2: l2-cache3 {
compatible = "cache"; compatible = "cache";
}; };
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
}; };
&pcie1 { &pcie1 {
......
arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
View file @ 39a71db1
...@@ -53,6 +53,7 @@ cpu0: cpu@0 { ...@@ -53,6 +53,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x0>; reg = <0x0>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -62,6 +63,7 @@ cpu1: cpu@1 { ...@@ -62,6 +63,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x1>; reg = <0x1>;
clocks = <&clockgen 1 0>; clocks = <&clockgen 1 0>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
}; };
...@@ -70,6 +72,7 @@ cpu2: cpu@100 { ...@@ -70,6 +72,7 @@ cpu2: cpu@100 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x100>; reg = <0x100>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -79,6 +82,7 @@ cpu3: cpu@101 { ...@@ -79,6 +82,7 @@ cpu3: cpu@101 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x101>; reg = <0x101>;
clocks = <&clockgen 1 1>; clocks = <&clockgen 1 1>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
}; };
...@@ -88,6 +92,7 @@ cpu4: cpu@200 { ...@@ -88,6 +92,7 @@ cpu4: cpu@200 {
reg = <0x200>; reg = <0x200>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -96,6 +101,7 @@ cpu5: cpu@201 { ...@@ -96,6 +101,7 @@ cpu5: cpu@201 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x201>; reg = <0x201>;
clocks = <&clockgen 1 2>; clocks = <&clockgen 1 2>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
}; };
...@@ -104,6 +110,7 @@ cpu6: cpu@300 { ...@@ -104,6 +110,7 @@ cpu6: cpu@300 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x300>; reg = <0x300>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
...@@ -113,6 +120,7 @@ cpu7: cpu@301 { ...@@ -113,6 +120,7 @@ cpu7: cpu@301 {
compatible = "arm,cortex-a72"; compatible = "arm,cortex-a72";
reg = <0x301>; reg = <0x301>;
clocks = <&clockgen 1 3>; clocks = <&clockgen 1 3>;
cpu-idle-states = <&CPU_PW20>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
}; };
...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 { ...@@ -131,6 +139,15 @@ cluster2_l2: l2-cache2 {
cluster3_l2: l2-cache3 { cluster3_l2: l2-cache3 {
compatible = "cache"; compatible = "cache";
}; };
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x00010000>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
}; };
&pcie1 { &pcie1 {
......
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View file @ 39a71db1
...@@ -125,6 +125,11 @@ pmu { ...@@ -125,6 +125,11 @@ pmu {
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
}; };
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <2>; #address-cells = <2>;
......
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