Commit 3a33467f authored by Gregory CLEMENT's avatar Gregory CLEMENT

ARM: dts: armada-375: Use the node labels

Use the node label when possible. As a result it flattens the device tree
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent e4a0709d
...@@ -69,15 +69,36 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 ...@@ -69,15 +69,36 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs { };
spi@10600 { };
&pciec {
status = "okay";
};
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
&pcie0 {
/* Port 0, Lane 0 */
status = "okay";
};
&pcie1 {
/* Port 1, Lane 0 */
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_pins>; pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
/* /*
* SPI conflicts with NAND, so we disable it * SPI conflicts with NAND, so we disable it here, and
* here, and select NAND as the enabled device * select NAND as the enabled device by default.
* by default.
*/ */
status = "disabled"; status = "disabled";
spi-flash@0 { spi-flash@0 {
...@@ -87,39 +108,39 @@ spi-flash@0 { ...@@ -87,39 +108,39 @@ spi-flash@0 {
reg = <0>; /* Chip select 0 */ reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>; spi-max-frequency = <108000000>;
}; };
}; };
i2c@11000 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>; pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
i2c@11100 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>; pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
serial@12000 { &uart0 {
status = "okay"; status = "okay";
}; };
pinctrl { &pinctrl {
sdio_st_pins: sdio-st-pins { sdio_st_pins: sdio-st-pins {
marvell,pins = "mpp44", "mpp45"; marvell,pins = "mpp44", "mpp45";
marvell,function = "gpio"; marvell,function = "gpio";
}; };
}; };
sata@a0000 { &sata {
status = "okay"; status = "okay";
nr-ports = <2>; nr-ports = <2>;
}; };
nand: nand@d0000 { &nand {
pinctrl-0 = <&nand_pins>; pinctrl-0 = <&nand_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
...@@ -142,25 +163,25 @@ partition@1000000 { ...@@ -142,25 +163,25 @@ partition@1000000 {
label = "Filesystem"; label = "Filesystem";
reg = <0x1000000 0x3f000000>; reg = <0x1000000 0x3f000000>;
}; };
}; };
usb@54000 { &usb1 {
status = "okay"; status = "okay";
}; };
usb3@58000 { &usb2 {
status = "okay"; status = "okay";
}; };
mvsdio@d4000 { &sdio {
pinctrl-0 = <&sdio_pins &sdio_st_pins>; pinctrl-0 = <&sdio_pins &sdio_st_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
}; };
mdio { &mdio {
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };
...@@ -168,39 +189,21 @@ phy0: ethernet-phy@0 { ...@@ -168,39 +189,21 @@ phy0: ethernet-phy@0 {
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
reg = <3>; reg = <3>;
}; };
}; };
ethernet@f0000 { &ethernet {
status = "okay"; status = "okay";
};
eth0@c4000 { &eth0 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
}; };
eth1@c5000 { &eth1 {
status = "okay"; status = "okay";
phy = <&phy3>; phy = <&phy3>;
phy-mode = "gmii"; phy-mode = "gmii";
};
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
}; };
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