Commit 3a7e4f56 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

wifi: rtw89: mac: define internal memory address for WiFi 7 chip

Define base address of WiFi 7 internal memory according to design to
provide the same functions as existing WiFi 6 chips.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230822125822.23817-4-pkshih@realtek.com
parent 60168f6c
...@@ -275,6 +275,7 @@ enum rtw89_mac_dbg_port_sel { ...@@ -275,6 +275,7 @@ enum rtw89_mac_dbg_port_sel {
/* SRAM mem dump */ /* SRAM mem dump */
#define R_AX_INDIR_ACCESS_ENTRY 0x40000 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
#define R_BE_INDIR_ACCESS_ENTRY 0x80000
#define AXIDMA_BASE_ADDR 0x18006000 #define AXIDMA_BASE_ADDR 0x18006000
#define STA_SCHED_BASE_ADDR 0x18808000 #define STA_SCHED_BASE_ADDR 0x18808000
...@@ -298,6 +299,31 @@ enum rtw89_mac_dbg_port_sel { ...@@ -298,6 +299,31 @@ enum rtw89_mac_dbg_port_sel {
#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000 #define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
#define CPU_LOCAL_BASE_ADDR 0x18003000 #define CPU_LOCAL_BASE_ADDR 0x18003000
#define WD_PAGE_BASE_ADDR_BE 0x0
#define CPU_LOCAL_BASE_ADDR_BE 0x18003000
#define AXIDMA_BASE_ADDR_BE 0x18006000
#define SHARED_BUF_BASE_ADDR_BE 0x18700000
#define DMAC_TBL_BASE_ADDR_BE 0x18800000
#define SHCUT_MACHDR_BASE_ADDR_BE 0x18800800
#define STA_SCHED_BASE_ADDR_BE 0x18818000
#define NAT25_CAM_BASE_ADDR_BE 0x18820000
#define RXPLD_FLTR_CAM_BASE_ADDR_BE 0x18823000
#define SEC_CAM_BASE_ADDR_BE 0x18824000
#define WOW_CAM_BASE_ADDR_BE 0x18828000
#define MLD_TBL_BASE_ADDR_BE 0x18829000
#define RX_CLSF_CAM_BASE_ADDR_BE 0x1882A000
#define CMAC_TBL_BASE_ADDR_BE 0x18840000
#define ADDR_CAM_BASE_ADDR_BE 0x18850000
#define BSSID_CAM_BASE_ADDR_BE 0x18858000
#define BA_CAM_BASE_ADDR_BE 0x18859000
#define BCN_IE_CAM0_BASE_ADDR_BE 0x18860000
#define TXDATA_FIFO_0_BASE_ADDR_BE 0x18861000
#define TXD_FIFO_0_BASE_ADDR_BE 0x18862000
#define BCN_IE_CAM1_BASE_ADDR_BE 0x18880000
#define TXDATA_FIFO_1_BASE_ADDR_BE 0x18881000
#define TXD_FIFO_1_BASE_ADDR_BE 0x18881800
#define DCPU_LOCAL_BASE_ADDR_BE 0x19C02000
#define CCTL_INFO_SIZE 32 #define CCTL_INFO_SIZE 32
enum rtw89_mac_mem_sel { enum rtw89_mac_mem_sel {
...@@ -322,6 +348,7 @@ enum rtw89_mac_mem_sel { ...@@ -322,6 +348,7 @@ enum rtw89_mac_mem_sel {
RTW89_MAC_MEM_BSSID_CAM, RTW89_MAC_MEM_BSSID_CAM,
RTW89_MAC_MEM_TXD_FIFO_0_V1, RTW89_MAC_MEM_TXD_FIFO_0_V1,
RTW89_MAC_MEM_TXD_FIFO_1_V1, RTW89_MAC_MEM_TXD_FIFO_1_V1,
RTW89_MAC_MEM_WD_PAGE,
/* keep last */ /* keep last */
RTW89_MAC_MEM_NUM, RTW89_MAC_MEM_NUM,
......
...@@ -3,8 +3,35 @@ ...@@ -3,8 +3,35 @@
*/ */
#include "mac.h" #include "mac.h"
#include "reg.h"
static const u32 rtw89_mac_mem_base_addrs_be[RTW89_MAC_MEM_NUM] = {
[RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR_BE,
[RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR_BE,
[RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR_BE,
[RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR_BE,
[RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR_BE,
[RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_SECURITY_CAM] = SEC_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR_BE,
[RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR_BE,
[RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR_BE,
[RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR_BE,
[RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR_BE,
[RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR_BE,
[RTW89_MAC_MEM_WD_PAGE] = WD_PAGE_BASE_ADDR_BE,
};
const struct rtw89_mac_gen_def rtw89_mac_gen_be = { const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
.band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET, .band1_offset = RTW89_MAC_BE_BAND_REG_OFFSET,
.filter_model_addr = R_BE_FILTER_MODEL_ADDR,
.indir_access_addr = R_BE_INDIR_ACCESS_ENTRY,
.mem_base_addrs = rtw89_mac_mem_base_addrs_be,
}; };
EXPORT_SYMBOL(rtw89_mac_gen_be); EXPORT_SYMBOL(rtw89_mac_gen_be);
...@@ -3625,6 +3625,8 @@ ...@@ -3625,6 +3625,8 @@
#define B_AX_GNT_BT_TX_SW_VAL BIT(1) #define B_AX_GNT_BT_TX_SW_VAL BIT(1)
#define B_AX_GNT_BT_TX_SW_CTRL BIT(0) #define B_AX_GNT_BT_TX_SW_CTRL BIT(0)
#define R_BE_FILTER_MODEL_ADDR 0x0C04
#define RR_MOD 0x00 #define RR_MOD 0x00
#define RR_MOD_V1 0x10000 #define RR_MOD_V1 0x10000
#define RR_MOD_IQK GENMASK(19, 4) #define RR_MOD_IQK GENMASK(19, 4)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment