Commit 3aaf33be authored by Russell King's avatar Russell King

ARM: avoid faulting on qemu

When qemu starts a kernel in a bare environment, the default SCR has
the AW and FW bits clear, which means that the kernel can't modify
the PSR A or PSR F bits, and means that FIQs and imprecise aborts are
always masked.

When running uboot under qemu, the AW and FW SCR bits are set, and the
kernel functions normally - and this is how real hardware behaves.

Fix this for qemu by ignoring the FIQ bit.

Fixes: 8bafae20 ("ARM: BUG if jumping to usermode address in kernel mode")
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent 8bafae20
...@@ -299,7 +299,7 @@ ...@@ -299,7 +299,7 @@
mov r2, sp mov r2, sp
ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
ldr lr, [r2, #\offset + S_PC]! @ get pc ldr lr, [r2, #\offset + S_PC]! @ get pc
tst r1, #0xcf tst r1, #PSR_I_BIT | 0x0f
bne 1f bne 1f
msr spsr_cxsf, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K) #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_32v6K)
...@@ -331,7 +331,7 @@ ...@@ -331,7 +331,7 @@
ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
ldr lr, [sp, #\offset + S_PC] @ get pc ldr lr, [sp, #\offset + S_PC] @ get pc
add sp, sp, #\offset + S_SP add sp, sp, #\offset + S_SP
tst r1, #0xcf tst r1, #PSR_I_BIT | 0x0f
bne 1f bne 1f
msr spsr_cxsf, r1 @ save in spsr_svc msr spsr_cxsf, r1 @ save in spsr_svc
......
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