Commit 3c6591e9 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/pm: drop the cache for enabled ppfeatures

The following scenarios make the driver cache for enabled ppfeatures
outdated and invalid:
  - Other tools interact with PMFW to change the enabled ppfeatures.
  - PMFW may enable/disable some features behind driver's back. E.g.
    for sienna_cichild, on gfxoff entering, PMFW will disable gfx
    related DPM features. All those are performed without driver's
    notice.
Also considering driver does not actually interact with PMFW such
frequently, the benefit brought by such cache is very limited.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7ade3ca9
......@@ -950,7 +950,6 @@ static int smu_sw_init(void *handle)
smu->pool_size = adev->pm.smu_prv_buffer_size;
smu->smu_feature.feature_num = SMU_FEATURE_MAX;
bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
mutex_init(&smu->message_lock);
......
......@@ -390,7 +390,6 @@ struct smu_feature
uint32_t feature_num;
DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
};
struct smu_clocks {
......
......@@ -798,27 +798,8 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu)
int smu_v11_0_system_features_control(struct smu_context *smu,
bool en)
{
struct smu_feature *feature = &smu->smu_feature;
uint64_t feature_mask;
int ret = 0;
ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
SMU_MSG_DisableAllSmuFeatures), NULL);
if (ret)
return ret;
bitmap_zero(feature->enabled, feature->feature_num);
if (en) {
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;
bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
feature->feature_num);
}
return ret;
return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
SMU_MSG_DisableAllSmuFeatures), NULL);
}
int smu_v11_0_notify_display_change(struct smu_context *smu)
......
......@@ -1947,27 +1947,13 @@ static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clock
static int vangogh_system_features_control(struct smu_context *smu, bool en)
{
struct amdgpu_device *adev = smu->adev;
struct smu_feature *feature = &smu->smu_feature;
uint64_t feature_mask;
int ret = 0;
if (adev->pm.fw_version >= 0x43f1700 && !en)
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
RLC_STATUS_OFF, NULL);
bitmap_zero(feature->enabled, feature->feature_num);
if (!en)
return ret;
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;
bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
feature->feature_num);
return 0;
return ret;
}
static int vangogh_post_smu_init(struct smu_context *smu)
......
......@@ -764,27 +764,8 @@ int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
int smu_v13_0_system_features_control(struct smu_context *smu,
bool en)
{
struct smu_feature *feature = &smu->smu_feature;
uint64_t feature_mask;
int ret = 0;
ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
SMU_MSG_DisableAllSmuFeatures), NULL);
if (ret)
return ret;
bitmap_zero(feature->enabled, feature->feature_num);
if (en) {
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;
bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
feature->feature_num);
}
return ret;
return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
SMU_MSG_DisableAllSmuFeatures), NULL);
}
int smu_v13_0_notify_display_change(struct smu_context *smu)
......
......@@ -195,27 +195,13 @@ static int yellow_carp_fini_smc_tables(struct smu_context *smu)
static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
{
struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
uint64_t feature_mask;
int ret = 0;
if (!en && !adev->in_s0ix)
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
bitmap_zero(feature->enabled, feature->feature_num);
if (!en)
return ret;
ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
if (ret)
return ret;
bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
feature->feature_num);
return 0;
return ret;
}
static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
......
......@@ -496,8 +496,8 @@ int smu_cmn_feature_is_supported(struct smu_context *smu,
int smu_cmn_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
uint64_t enabled_features;
int feature_id;
if (smu->is_apu && adev->family < AMDGPU_FAMILY_VGH)
......@@ -509,9 +509,12 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
if (feature_id < 0)
return 0;
WARN_ON(feature_id > feature->feature_num);
if (smu_cmn_get_enabled_mask(smu, &enabled_features)) {
dev_err(adev->dev, "Failed to retrieve enabled ppfeatures!\n");
return 0;
}
return test_bit(feature_id, feature->enabled);
return test_bit(feature_id, (unsigned long *)&enabled_features);
}
bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
......@@ -544,7 +547,6 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint64_t *feature_mask)
{
struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
uint32_t *feature_mask_high;
uint32_t *feature_mask_low;
......@@ -553,13 +555,6 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
if (!feature_mask)
return -EINVAL;
if (!bitmap_empty(feature->enabled, feature->feature_num)) {
bitmap_copy((unsigned long *)feature_mask,
feature->enabled,
feature->feature_num);
return 0;
}
feature_mask_low = &((uint32_t *)feature_mask)[0];
feature_mask_high = &((uint32_t *)feature_mask)[1];
......@@ -616,7 +611,6 @@ int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled)
{
struct smu_feature *feature = &smu->smu_feature;
int ret = 0;
if (enabled) {
......@@ -630,8 +624,6 @@ int smu_cmn_feature_update_enable_state(struct smu_context *smu,
SMU_MSG_EnableSmuFeaturesHigh,
upper_32_bits(feature_mask),
NULL);
if (ret)
return ret;
} else {
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_DisableSmuFeaturesLow,
......@@ -643,17 +635,8 @@ int smu_cmn_feature_update_enable_state(struct smu_context *smu,
SMU_MSG_DisableSmuFeaturesHigh,
upper_32_bits(feature_mask),
NULL);
if (ret)
return ret;
}
if (enabled)
bitmap_or(feature->enabled, feature->enabled,
(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
else
bitmap_andnot(feature->enabled, feature->enabled,
(unsigned long *)(&feature_mask), SMU_FEATURE_MAX);
return ret;
}
......@@ -661,7 +644,6 @@ int smu_cmn_feature_set_enabled(struct smu_context *smu,
enum smu_feature_mask mask,
bool enable)
{
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
feature_id = smu_cmn_to_asic_specific_index(smu,
......@@ -670,8 +652,6 @@ int smu_cmn_feature_set_enabled(struct smu_context *smu,
if (feature_id < 0)
return -EINVAL;
WARN_ON(feature_id > feature->feature_num);
return smu_cmn_feature_update_enable_state(smu,
1ULL << feature_id,
enable);
......@@ -793,7 +773,6 @@ int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
bool no_hw_disablement,
enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
uint64_t features_to_disable = U64_MAX;
int skipped_feature_id;
......@@ -807,15 +786,12 @@ int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
features_to_disable &= ~(1ULL << skipped_feature_id);
}
if (no_hw_disablement) {
bitmap_andnot(feature->enabled, feature->enabled,
(unsigned long *)(&features_to_disable), SMU_FEATURE_MAX);
if (no_hw_disablement)
return 0;
} else {
return smu_cmn_feature_update_enable_state(smu,
features_to_disable,
0);
}
return smu_cmn_feature_update_enable_state(smu,
features_to_disable,
0);
}
int smu_cmn_get_smc_version(struct smu_context *smu,
......
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