Commit 3c678552 authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson

arm64: dts: qcom: sm8450: Add video clock controller

Add device node for video clock controller on Qualcomm SM8450 platform.
Signed-off-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-4-quic_tdas@quicinc.com
parent e23893db
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h> #include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include <dt-bindings/clock/qcom,sm8450-dispcc.h> #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/mailbox/qcom-ipcc.h>
...@@ -2598,6 +2599,18 @@ IPCC_MPROC_SIGNAL_GLINK_QMP ...@@ -2598,6 +2599,18 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
}; };
}; };
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8450-videocc";
reg = <0 0x0aaf0000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
cci0: cci@ac15000 { cci0: cci@ac15000 {
compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
reg = <0 0x0ac15000 0 0x1000>; reg = <0 0x0ac15000 0 0x1000>;
......
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