Commit 3cc41541 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson

arm64: dts: qcom: sm6350: Add cpufreq-hw support

Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable
CPU clock scaling.
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org
parent 23737b95
......@@ -42,6 +42,7 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
......@@ -60,6 +61,7 @@ CPU1: cpu@100 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
......@@ -75,6 +77,7 @@ CPU2: cpu@200 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
......@@ -90,6 +93,7 @@ CPU3: cpu@300 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
......@@ -105,6 +109,7 @@ CPU4: cpu@400 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
......@@ -120,6 +125,7 @@ CPU5: cpu@500 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
......@@ -136,6 +142,7 @@ CPU6: cpu@600 {
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
......@@ -151,6 +158,7 @@ CPU7: cpu@700 {
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
......@@ -621,6 +629,16 @@ rpmhcc: clock-controller {
clocks = <&xo_board>;
};
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
timer {
......
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