drm/amdgpu/powerplay: add thermal control interface in hwmgr.

BugLink: http://bugs.launchpad.net/bugs/1546572

Thermal controller interface.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit fba4eef5)
Signed-off-by: Alberto Milone <alberto.milone@canonical.com>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

@@ -194,3 +194,32 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
 
     return 0;
 }
+
+int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
+{
+	if (hwmgr == NULL || hwmgr->hwmgr_func->stop_thermal_controller == NULL)
+		return -EINVAL;
+
+	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
+}
+
+int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info)
+{
+	if (hwmgr == NULL || hwmgr->hwmgr_func->register_internal_thermal_interrupt == NULL)
+		return -EINVAL;
+
+	return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info);
+}
+
+/**
+* Initializes the thermal controller subsystem.
+*
+* @param    pHwMgr  the address of the powerplay hardware manager.
+* @param    pTemperatureRange the address of the structure holding the temperature range.
+* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
+*/
+int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range)
+{
+
+	return phm_dispatch_table(hwmgr, &(hwmgr->start_thermal_controller), temperature_range, NULL);
+}

drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

@@ -29,6 +29,18 @@ struct pp_hwmgr;
 struct pp_hw_power_state;
 struct pp_power_state;
 enum amd_dpm_forced_level;
+struct PP_TemperatureRange;
+
+struct phm_fan_speed_info {
+	uint32_t min_percent;
+	uint32_t max_percent;
+	uint32_t min_rpm;
+	uint32_t max_rpm;
+	bool supports_percent_read;
+	bool supports_percent_write;
+	bool supports_rpm_read;
+	bool supports_rpm_write;
+};
 
 /* Automatic Power State Throttling */
 enum PHM_AutoThrottleSource
@@ -330,4 +342,8 @@ extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
 extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
 extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
+extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
+extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
+extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
 #endif /* _HARDWARE_MANAGER_H_ */
+

drivers/gpu/drm/amd/powerplay/inc/power_state.h

@@ -122,8 +122,8 @@ struct PP_StateSoftwareAlgorithmBlock {
  * Type to hold a temperature range.
  */
 struct PP_TemperatureRange {
-	uint16_t min;
-	uint16_t max;
+	uint32_t min;
+	uint32_t max;
 };
 
 struct PP_StateValidationBlock {