Commit 3d02352c authored by Rodrigo Vivi's avatar Rodrigo Vivi

drm/i915/cnp: add CNP gmbus support

On CNP PCH based platforms the gmbus is on the south display that
is on PCH. The existing implementation for previous platforms
already covers the need for CNP expect for the pin pair configuration
that follows similar definitions that we had on BXT.

v2: Don't drop "_BXT" as the indicator of the first platform
    supporting this pin numbers. Suggested by Daniel.
v3: Add missing else and fix register table since CNP GPIO_CTL
    starts on 0xC5014.
v4: Fix pin number and map according to the current available VBT.
    Re-add pin 4 for port D. Lost during some rebase.
v5: Use table as spec. If VBT is wrong it should be ignored.

Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-5-git-send-email-rodrigo.vivi@intel.com
parent 4c9f7086
...@@ -2626,9 +2626,10 @@ enum skl_disp_power_wells { ...@@ -2626,9 +2626,10 @@ enum skl_disp_power_wells {
#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */ #define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
#define GMBUS_PIN_DPD 6 /* HDMID */ #define GMBUS_PIN_DPD 6 /* HDMID */
#define GMBUS_PIN_RESERVED 7 /* 7 reserved */ #define GMBUS_PIN_RESERVED 7 /* 7 reserved */
#define GMBUS_PIN_1_BXT 1 #define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
#define GMBUS_PIN_2_BXT 2 #define GMBUS_PIN_2_BXT 2
#define GMBUS_PIN_3_BXT 3 #define GMBUS_PIN_3_BXT 3
#define GMBUS_PIN_4_CNP 4
#define GMBUS_NUM_PINS 7 /* including 0 */ #define GMBUS_NUM_PINS 7 /* including 0 */
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1<<31) #define GMBUS_SW_CLR_INT (1<<31)
......
...@@ -1802,19 +1802,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, ...@@ -1802,19 +1802,21 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
switch (port) { switch (port) {
case PORT_B: case PORT_B:
if (IS_GEN9_LP(dev_priv)) if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_1_BXT; ddc_pin = GMBUS_PIN_1_BXT;
else else
ddc_pin = GMBUS_PIN_DPB; ddc_pin = GMBUS_PIN_DPB;
break; break;
case PORT_C: case PORT_C:
if (IS_GEN9_LP(dev_priv)) if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_2_BXT; ddc_pin = GMBUS_PIN_2_BXT;
else else
ddc_pin = GMBUS_PIN_DPC; ddc_pin = GMBUS_PIN_DPC;
break; break;
case PORT_D: case PORT_D:
if (IS_CHERRYVIEW(dev_priv)) if (HAS_PCH_CNP(dev_priv))
ddc_pin = GMBUS_PIN_4_CNP;
else if (IS_CHERRYVIEW(dev_priv))
ddc_pin = GMBUS_PIN_DPD_CHV; ddc_pin = GMBUS_PIN_DPD_CHV;
else else
ddc_pin = GMBUS_PIN_DPD; ddc_pin = GMBUS_PIN_DPD;
......
...@@ -68,11 +68,20 @@ static const struct gmbus_pin gmbus_pins_bxt[] = { ...@@ -68,11 +68,20 @@ static const struct gmbus_pin gmbus_pins_bxt[] = {
[GMBUS_PIN_3_BXT] = { "misc", GPIOD }, [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
}; };
static const struct gmbus_pin gmbus_pins_cnp[] = {
[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
};
/* pin is expected to be valid */ /* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin) unsigned int pin)
{ {
if (IS_GEN9_LP(dev_priv)) if (HAS_PCH_CNP(dev_priv))
return &gmbus_pins_cnp[pin];
else if (IS_GEN9_LP(dev_priv))
return &gmbus_pins_bxt[pin]; return &gmbus_pins_bxt[pin];
else if (IS_GEN9_BC(dev_priv)) else if (IS_GEN9_BC(dev_priv))
return &gmbus_pins_skl[pin]; return &gmbus_pins_skl[pin];
...@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, ...@@ -87,7 +96,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
{ {
unsigned int size; unsigned int size;
if (IS_GEN9_LP(dev_priv)) if (HAS_PCH_CNP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_cnp);
else if (IS_GEN9_LP(dev_priv))
size = ARRAY_SIZE(gmbus_pins_bxt); size = ARRAY_SIZE(gmbus_pins_bxt);
else if (IS_GEN9_BC(dev_priv)) else if (IS_GEN9_BC(dev_priv))
size = ARRAY_SIZE(gmbus_pins_skl); size = ARRAY_SIZE(gmbus_pins_skl);
......
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