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Commit 3dc95666 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits)
  MIPS: BCM63xx: Add integrated ethernet mac support.
  MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.
  MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.
  MIPS: Octeon:  Move some platform device registration to its own file.
  MIPS: Don't corrupt page tables on vmalloc fault.
  MIPS: Shrink the size of tlb handler
  MIPS: Alchemy: override loops_per_jiffy detection
  MIPS: hw_random: Add hardware RNG for Octeon SOCs.
  MIPS: Octeon:  Add hardware RNG platform device.
  MIPS: Remove useless zero initializations.
  MIPS: Alchemy: get rid of allow_au1k_wait
  MIPS: Octeon: Set kernel_uses_llsc to false on non-SMP builds.
  MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.
  MIPS: Get rid of CONFIG_CPU_HAS_LLSC
  MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC
  MIPS: Rewrite clearing of ll_bit on context switch in C
  MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler
  MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file.
  MIPS: Clean up linker script using new linker script macros.
  MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE.
  ...
parents b938fb6f 9b1fc55a
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Showing with 10390 additions and 1238 deletions
Documentation/kernel-parameters.txt
View file @ 3dc95666
......@@ -1286,6 +1286,10 @@ and is between 256 and 4096 characters. It is defined in the file
(machvec) in a generic kernel.
Example: machvec=hpzx1_swiotlb
machtype= [Loongson] Share the same kernel image file between different
yeeloong laptop.
Example: machtype=lemote-yeeloong-2f-7inch
max_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory greater
than or equal to this physical address is ignored.
......
arch/mips/Kconfig
View file @ 3dc95666
......@@ -6,7 +6,7 @@ config MIPS
select HAVE_ARCH_KGDB
# Horrible source of confusion. Die, die, die ...
select EMBEDDED
select RTC_LIB
select RTC_LIB if !LEMOTE_FULOONG2E
mainmenu "Linux/MIPS Kernel Configuration"
......@@ -80,6 +80,21 @@ config BCM47XX
help
Support for BCM47XX based boards
config BCM63XX
bool "Broadcom BCM63XX based boards"
select CEVT_R4K
select CSRC_R4K
select DMA_NONCOHERENT
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_HAS_EARLY_PRINTK
select SWAP_IO_SPACE
select ARCH_REQUIRE_GPIOLIB
help
Support for BCM63XX based boards
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
......@@ -174,30 +189,15 @@ config LASAT
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
select SYS_SUPPORTS_LITTLE_ENDIAN
config LEMOTE_FULONG
bool "Lemote Fulong mini-PC"
select ARCH_SPARSEMEM_ENABLE
select CEVT_R4K
select CSRC_R4K
select SYS_HAS_CPU_LOONGSON2
select DMA_NONCOHERENT
select BOOT_ELF32
select BOARD_SCACHE
select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_PCI
select I8259
select ISA
select IRQ_CPU
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
select GENERIC_ISA_DMA_SUPPORT_BROKEN
select CPU_HAS_WB
config MACH_LOONGSON
bool "Loongson family of machines"
help
Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
an FPGA northbridge
This enables the support of Loongson family of machines.
Loongson is a family of general-purpose MIPS-compatible CPUs.
developed at Institute of Computing Technology (ICT),
Chinese Academy of Sciences (CAS) in the People's Republic
of China. The chief architect is Professor Weiwu Hu.
config MIPS_MALTA
bool "MIPS Malta board"
......@@ -660,6 +660,7 @@ endchoice
source "arch/mips/alchemy/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
......@@ -668,6 +669,7 @@ source "arch/mips/sibyte/Kconfig"
source "arch/mips/txx9/Kconfig"
source "arch/mips/vr41xx/Kconfig"
source "arch/mips/cavium-octeon/Kconfig"
source "arch/mips/loongson/Kconfig"
endmenu
......@@ -1044,12 +1046,10 @@ choice
prompt "CPU type"
default CPU_R4X00
config CPU_LOONGSON2
bool "Loongson 2"
depends on SYS_HAS_CPU_LOONGSON2
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
config CPU_LOONGSON2E
bool "Loongson 2E"
depends on SYS_HAS_CPU_LOONGSON2E
select CPU_LOONGSON2
help
The Loongson 2E processor implements the MIPS III instruction set
with many extensions.
......@@ -1057,7 +1057,6 @@ config CPU_LOONGSON2
config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
......@@ -1075,7 +1074,6 @@ config CPU_MIPS32_R1
config CPU_MIPS32_R2
bool "MIPS32 Release 2"
depends on SYS_HAS_CPU_MIPS32_R2
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
......@@ -1089,7 +1087,6 @@ config CPU_MIPS32_R2
config CPU_MIPS64_R1
bool "MIPS64 Release 1"
depends on SYS_HAS_CPU_MIPS64_R1
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1109,7 +1106,6 @@ config CPU_MIPS64_R1
config CPU_MIPS64_R2
bool "MIPS64 Release 2"
depends on SYS_HAS_CPU_MIPS64_R2
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1155,7 +1151,6 @@ config CPU_VR41XX
config CPU_R4300
bool "R4300"
depends on SYS_HAS_CPU_R4300
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1164,7 +1159,6 @@ config CPU_R4300
config CPU_R4X00
bool "R4x00"
depends on SYS_HAS_CPU_R4X00
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1174,7 +1168,6 @@ config CPU_R4X00
config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1182,7 +1175,6 @@ config CPU_TX49XX
config CPU_R5000
bool "R5000"
depends on SYS_HAS_CPU_R5000
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1191,14 +1183,12 @@ config CPU_R5000
config CPU_R5432
bool "R5432"
depends on SYS_HAS_CPU_R5432
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
config CPU_R5500
bool "R5500"
depends on SYS_HAS_CPU_R5500
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
......@@ -1209,7 +1199,6 @@ config CPU_R5500
config CPU_R6000
bool "R6000"
depends on EXPERIMENTAL
select CPU_HAS_LLSC
depends on SYS_HAS_CPU_R6000
select CPU_SUPPORTS_32BIT_KERNEL
help
......@@ -1219,7 +1208,6 @@ config CPU_R6000
config CPU_NEVADA
bool "RM52xx"
depends on SYS_HAS_CPU_NEVADA
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1229,7 +1217,6 @@ config CPU_R8000
bool "R8000"
depends on EXPERIMENTAL
depends on SYS_HAS_CPU_R8000
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_64BIT_KERNEL
help
......@@ -1239,7 +1226,6 @@ config CPU_R8000
config CPU_R10000
bool "R10000"
depends on SYS_HAS_CPU_R10000
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1250,7 +1236,6 @@ config CPU_R10000
config CPU_RM7000
bool "RM7000"
depends on SYS_HAS_CPU_RM7000
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1259,7 +1244,6 @@ config CPU_RM7000
config CPU_RM9000
bool "RM9000"
depends on SYS_HAS_CPU_RM9000
select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
......@@ -1269,7 +1253,6 @@ config CPU_RM9000
config CPU_SB1
bool "SB1"
depends on SYS_HAS_CPU_SB1
select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
......@@ -1296,7 +1279,13 @@ config CPU_CAVIUM_OCTEON
endchoice
config SYS_HAS_CPU_LOONGSON2
config CPU_LOONGSON2
bool
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
config SYS_HAS_CPU_LOONGSON2E
bool
config SYS_HAS_CPU_MIPS32_R1
......@@ -1683,9 +1672,6 @@ config SB1_PASS_2_1_WORKAROUNDS
config 64BIT_PHYS_ADDR
bool
config CPU_HAS_LLSC
bool
config CPU_HAS_SMARTMIPS
depends on SYS_SUPPORTS_SMARTMIPS
bool "Support for the SmartMIPS ASE"
......
arch/mips/Makefile
View file @ 3dc95666
......@@ -120,7 +120,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
# only gcc >= 4.4 have the loongson-specific support
cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
cflags-$(CONFIG_CPU_LOONGSON2E) += \
$(call cc-option,-march=loongson2e,-march=r4600)
cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
-Wa,-mips32 -Wa,--trap
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
......@@ -314,11 +318,12 @@ cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
#
# lemote fulong mini-PC board
# Loongson family
#
core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/
load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000
cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote
core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
-mno-branch-likely
load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
#
# MIPS Malta board
......@@ -559,6 +564,13 @@ core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
load-$(CONFIG_BCM47XX) := 0xffffffff80001000
#
# Broadcom BCM63XX boards
#
core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
load-$(CONFIG_BCM63XX) := 0xffffffff80010000
#
# SNI RM
#
......
arch/mips/alchemy/common/setup.c
View file @ 3dc95666
......@@ -27,6 +27,7 @@
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/pm.h>
......@@ -53,6 +54,9 @@ void __init plat_mem_setup(void)
printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
/* this is faster than wasting cycles trying to approximate it */
preset_lpj = (est_freq >> 1) / HZ;
_machine_restart = au1000_restart;
_machine_halt = au1000_halt;
pm_power_off = au1000_power_off;
......
arch/mips/alchemy/common/time.c
View file @ 3dc95666
......@@ -36,14 +36,13 @@
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <asm/processor.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>
/* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
extern int allow_au1k_wait; /* default off for CP0 Counter */
static cycle_t au1x_counter1_read(struct clocksource *cs)
{
return au_readl(SYS_RTCREAD);
......@@ -153,13 +152,17 @@ void __init plat_time_init(void)
printk(KERN_INFO "Alchemy clocksource installed\n");
/* can now use 'wait' */
allow_au1k_wait = 1;
return;
cntr_err:
/* counters unusable, use C0 counter */
/*
* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
* function is called. Because the Alchemy counters are unusable
* the C0 timekeeping code is installed and use of the 'wait'
* instruction must be prohibited, which is done most easily by
* assigning NULL to cpu_wait.
*/
cpu_wait = NULL;
r4k_clockevent_init();
init_r4k_clocksource();
allow_au1k_wait = 0;
}
arch/mips/ar7/platform.c
View file @ 3dc95666
......@@ -417,6 +417,20 @@ static struct platform_device ar7_udc = {
.num_resources = ARRAY_SIZE(usb_res),
};
static struct resource ar7_wdt_res = {
.name = "regs",
.start = -1, /* Filled at runtime */
.end = -1, /* Filled at runtime */
.flags = IORESOURCE_MEM,
};
static struct platform_device ar7_wdt = {
.id = -1,
.name = "ar7_wdt",
.resource = &ar7_wdt_res,
.num_resources = 1,
};
static inline unsigned char char2hex(char h)
{
switch (h) {
......@@ -487,6 +501,7 @@ static void __init detect_leds(void)
static int __init ar7_register_devices(void)
{
u16 chip_id;
int res;
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port[2];
......@@ -565,6 +580,23 @@ static int __init ar7_register_devices(void)
res = platform_device_register(&ar7_udc);
chip_id = ar7_chip_id();
switch (chip_id) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
ar7_wdt_res.start = AR7_REGS_WDT;
break;
case AR7_CHIP_7300:
ar7_wdt_res.start = UR8_REGS_WDT;
break;
default:
break;
}
ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
res = platform_device_register(&ar7_wdt);
return res;
}
arch_initcall(ar7_register_devices);
arch/mips/bcm63xx/Kconfig 0 → 100644
View file @ 3dc95666
menu "CPU support"
depends on BCM63XX
config BCM63XX_CPU_6338
bool "support 6338 CPU"
select HW_HAS_PCI
select USB_ARCH_HAS_OHCI
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6345
bool "support 6345 CPU"
select USB_OHCI_BIG_ENDIAN_DESC
select USB_OHCI_BIG_ENDIAN_MMIO
config BCM63XX_CPU_6348
bool "support 6348 CPU"
select HW_HAS_PCI
config BCM63XX_CPU_6358
bool "support 6358 CPU"
select HW_HAS_PCI
endmenu
source "arch/mips/bcm63xx/boards/Kconfig"
arch/mips/bcm63xx/Makefile 0 → 100644
View file @ 3dc95666
obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
dev-dsp.o dev-enet.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-y += boards/
EXTRA_CFLAGS += -Werror
arch/mips/bcm63xx/boards/Kconfig 0 → 100644
View file @ 3dc95666
choice
prompt "Board support"
depends on BCM63XX
default BOARD_BCM963XX
config BOARD_BCM963XX
bool "Generic Broadcom 963xx boards"
select SSB
help
endchoice
arch/mips/bcm63xx/boards/Makefile 0 → 100644
View file @ 3dc95666
obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o
EXTRA_CFLAGS += -Werror
arch/mips/bcm63xx/boards/board_bcm963xx.c 0 → 100644
View file @ 3dc95666
This diff is collapsed.
arch/mips/bcm63xx/clk.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_clk.h>
static DEFINE_MUTEX(clocks_mutex);
static void clk_enable_unlocked(struct clk *clk)
{
if (clk->set && (clk->usage++) == 0)
clk->set(clk, 1);
}
static void clk_disable_unlocked(struct clk *clk)
{
if (clk->set && (--clk->usage) == 0)
clk->set(clk, 0);
}
static void bcm_hwclock_set(u32 mask, int enable)
{
u32 reg;
reg = bcm_perf_readl(PERF_CKCTL_REG);
if (enable)
reg |= mask;
else
reg &= ~mask;
bcm_perf_writel(reg, PERF_CKCTL_REG);
}
/*
* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
*/
static void enet_misc_set(struct clk *clk, int enable)
{
u32 mask;
if (BCMCPU_IS_6338())
mask = CKCTL_6338_ENET_EN;
else if (BCMCPU_IS_6345())
mask = CKCTL_6345_ENET_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ENET_EN;
else
/* BCMCPU_IS_6358 */
mask = CKCTL_6358_EMUSB_EN;
bcm_hwclock_set(mask, enable);
}
static struct clk clk_enet_misc = {
.set = enet_misc_set,
};
/*
* Ethernet MAC clocks: only revelant on 6358, silently enable misc
* clocks
*/
static void enetx_set(struct clk *clk, int enable)
{
if (enable)
clk_enable_unlocked(&clk_enet_misc);
else
clk_disable_unlocked(&clk_enet_misc);
if (BCMCPU_IS_6358()) {
u32 mask;
if (clk->id == 0)
mask = CKCTL_6358_ENET0_EN;
else
mask = CKCTL_6358_ENET1_EN;
bcm_hwclock_set(mask, enable);
}
}
static struct clk clk_enet0 = {
.id = 0,
.set = enetx_set,
};
static struct clk clk_enet1 = {
.id = 1,
.set = enetx_set,
};
/*
* Ethernet PHY clock
*/
static void ephy_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
}
static struct clk clk_ephy = {
.set = ephy_set,
};
/*
* PCM clock
*/
static void pcm_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6358())
return;
bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
}
static struct clk clk_pcm = {
.set = pcm_set,
};
/*
* USB host clock
*/
static void usbh_set(struct clk *clk, int enable)
{
if (!BCMCPU_IS_6348())
return;
bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
}
static struct clk clk_usbh = {
.set = usbh_set,
};
/*
* SPI clock
*/
static void spi_set(struct clk *clk, int enable)
{
u32 mask;
if (BCMCPU_IS_6338())
mask = CKCTL_6338_SPI_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_SPI_EN;
else
/* BCMCPU_IS_6358 */
mask = CKCTL_6358_SPI_EN;
bcm_hwclock_set(mask, enable);
}
static struct clk clk_spi = {
.set = spi_set,
};
/*
* Internal peripheral clock
*/
static struct clk clk_periph = {
.rate = (50 * 1000 * 1000),
};
/*
* Linux clock API implementation
*/
int clk_enable(struct clk *clk)
{
mutex_lock(&clocks_mutex);
clk_enable_unlocked(clk);
mutex_unlock(&clocks_mutex);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
mutex_lock(&clocks_mutex);
clk_disable_unlocked(clk);
mutex_unlock(&clocks_mutex);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "enet0"))
return &clk_enet0;
if (!strcmp(id, "enet1"))
return &clk_enet1;
if (!strcmp(id, "ephy"))
return &clk_ephy;
if (!strcmp(id, "usbh"))
return &clk_usbh;
if (!strcmp(id, "spi"))
return &clk_spi;
if (!strcmp(id, "periph"))
return &clk_periph;
if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
return &clk_pcm;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
arch/mips/bcm63xx/cpu.c 0 → 100644
View file @ 3dc95666
This diff is collapsed.
arch/mips/bcm63xx/cs.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/log2.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_cs.h>
static DEFINE_SPINLOCK(bcm63xx_cs_lock);
/*
* check if given chip select exists
*/
static int is_valid_cs(unsigned int cs)
{
if (cs > 6)
return 0;
return 1;
}
/*
* Configure chipselect base address and size (bytes).
* Size must be a power of two between 8k and 256M.
*/
int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
/* sanity check on size */
if (size != roundup_pow_of_two(size))
return -EINVAL;
if (size < 8 * 1024 || size > 256 * 1024 * 1024)
return -EINVAL;
val = (base & MPI_CSBASE_BASE_MASK);
/* 8k => 0 - 256M => 15 */
val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_base);
/*
* configure chipselect timing (ns)
*/
int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
unsigned int setup, unsigned int hold)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
val &= ~(MPI_CSCTL_WAIT_MASK);
val &= ~(MPI_CSCTL_SETUP_MASK);
val &= ~(MPI_CSCTL_HOLD_MASK);
val |= wait << MPI_CSCTL_WAIT_SHIFT;
val |= setup << MPI_CSCTL_SETUP_SHIFT;
val |= hold << MPI_CSCTL_HOLD_SHIFT;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_timing);
/*
* configure other chipselect parameter (data bus size, ...)
*/
int bcm63xx_set_cs_param(unsigned int cs, u32 params)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
/* none of this fields apply to pcmcia */
if (cs == MPI_CS_PCMCIA_COMMON ||
cs == MPI_CS_PCMCIA_ATTR ||
cs == MPI_CS_PCMCIA_IO)
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
val &= ~(MPI_CSCTL_DATA16_MASK);
val &= ~(MPI_CSCTL_SYNCMODE_MASK);
val &= ~(MPI_CSCTL_TSIZE_MASK);
val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
val |= params;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_param);
/*
* set cs status (enable/disable)
*/
int bcm63xx_set_cs_status(unsigned int cs, int enable)
{
unsigned long flags;
u32 val;
if (!is_valid_cs(cs))
return -EINVAL;
spin_lock_irqsave(&bcm63xx_cs_lock, flags);
val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
if (enable)
val |= MPI_CSCTL_ENABLE_MASK;
else
val &= ~MPI_CSCTL_ENABLE_MASK;
bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_set_cs_status);
arch/mips/bcm63xx/dev-dsp.c 0 → 100644
View file @ 3dc95666
/*
* Broadcom BCM63xx VoIP DSP registration
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_dsp.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
static struct resource voip_dsp_resources[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bcm63xx_voip_dsp_device = {
.name = "bcm63xx-voip-dsp",
.id = 0,
.num_resources = ARRAY_SIZE(voip_dsp_resources),
.resource = voip_dsp_resources,
};
int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd)
{
struct bcm63xx_dsp_platform_data *dpd;
u32 val;
/* Get the memory window */
val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1));
val &= MPI_CSBASE_BASE_MASK;
voip_dsp_resources[0].start = val;
voip_dsp_resources[0].end = val + 0xFFFFFFF;
voip_dsp_resources[1].start = pd->ext_irq;
/* copy given platform data */
dpd = bcm63xx_voip_dsp_device.dev.platform_data;
memcpy(dpd, pd, sizeof (*pd));
return platform_device_register(&bcm63xx_voip_dsp_device);
}
arch/mips/bcm63xx/dev-enet.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_dev_enet.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
static struct resource shared_res[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
};
static struct platform_device bcm63xx_enet_shared_device = {
.name = "bcm63xx_enet_shared",
.id = 0,
.num_resources = ARRAY_SIZE(shared_res),
.resource = shared_res,
};
static int shared_device_registered;
static struct resource enet0_res[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct bcm63xx_enet_platform_data enet0_pd;
static struct platform_device bcm63xx_enet0_device = {
.name = "bcm63xx_enet",
.id = 0,
.num_resources = ARRAY_SIZE(enet0_res),
.resource = enet0_res,
.dev = {
.platform_data = &enet0_pd,
},
};
static struct resource enet1_res[] = {
{
.start = -1, /* filled at runtime */
.end = -1, /* filled at runtime */
.flags = IORESOURCE_MEM,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
{
.start = -1, /* filled at runtime */
.flags = IORESOURCE_IRQ,
},
};
static struct bcm63xx_enet_platform_data enet1_pd;
static struct platform_device bcm63xx_enet1_device = {
.name = "bcm63xx_enet",
.id = 1,
.num_resources = ARRAY_SIZE(enet1_res),
.resource = enet1_res,
.dev = {
.platform_data = &enet1_pd,
},
};
int __init bcm63xx_enet_register(int unit,
const struct bcm63xx_enet_platform_data *pd)
{
struct platform_device *pdev;
struct bcm63xx_enet_platform_data *dpd;
int ret;
if (unit > 1)
return -ENODEV;
if (!shared_device_registered) {
shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
shared_res[0].end = shared_res[0].start;
if (BCMCPU_IS_6338())
shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1;
else
shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
ret = platform_device_register(&bcm63xx_enet_shared_device);
if (ret)
return ret;
shared_device_registered = 1;
}
if (unit == 0) {
enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
enet0_res[0].end = enet0_res[0].start;
enet0_res[0].end += RSET_ENET_SIZE - 1;
enet0_res[1].start = bcm63xx_get_irq_number(IRQ_ENET0);
enet0_res[2].start = bcm63xx_get_irq_number(IRQ_ENET0_RXDMA);
enet0_res[3].start = bcm63xx_get_irq_number(IRQ_ENET0_TXDMA);
pdev = &bcm63xx_enet0_device;
} else {
enet1_res[0].start = bcm63xx_regset_address(RSET_ENET1);
enet1_res[0].end = enet1_res[0].start;
enet1_res[0].end += RSET_ENET_SIZE - 1;
enet1_res[1].start = bcm63xx_get_irq_number(IRQ_ENET1);
enet1_res[2].start = bcm63xx_get_irq_number(IRQ_ENET1_RXDMA);
enet1_res[3].start = bcm63xx_get_irq_number(IRQ_ENET1_TXDMA);
pdev = &bcm63xx_enet1_device;
}
/* copy given platform data */
dpd = pdev->dev.platform_data;
memcpy(dpd, pd, sizeof(*pd));
/* adjust them in case internal phy is used */
if (dpd->use_internal_phy) {
/* internal phy only exists for enet0 */
if (unit == 1)
return -ENODEV;
dpd->phy_id = 1;
dpd->has_phy_interrupt = 1;
dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY);
}
ret = platform_device_register(pdev);
if (ret)
return ret;
return 0;
}
arch/mips/bcm63xx/early_printk.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
static void __init wait_xfered(void)
{
unsigned int val;
/* wait for any previous char to be transmitted */
do {
val = bcm_uart0_readl(UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_TXEMPTY))
break;
} while (1);
}
void __init prom_putchar(char c)
{
wait_xfered();
bcm_uart0_writel(c, UART_FIFO_REG);
wait_xfered();
}
arch/mips/bcm63xx/gpio.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_gpio.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
static u32 gpio_out_low, gpio_out_high;
static void bcm63xx_gpio_set(struct gpio_chip *chip,
unsigned gpio, int val)
{
u32 reg;
u32 mask;
u32 *v;
unsigned long flags;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
mask = 1 << gpio;
v = &gpio_out_low;
} else {
reg = GPIO_DATA_HI_REG;
mask = 1 << (gpio - 32);
v = &gpio_out_high;
}
spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
if (val)
*v |= mask;
else
*v &= ~mask;
bcm_gpio_writel(*v, reg);
spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
}
static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
u32 reg;
u32 mask;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_DATA_LO_REG;
mask = 1 << gpio;
} else {
reg = GPIO_DATA_HI_REG;
mask = 1 << (gpio - 32);
}
return !!(bcm_gpio_readl(reg) & mask);
}
static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
unsigned gpio, int dir)
{
u32 reg;
u32 mask;
u32 tmp;
unsigned long flags;
if (gpio >= chip->ngpio)
BUG();
if (gpio < 32) {
reg = GPIO_CTL_LO_REG;
mask = 1 << gpio;
} else {
reg = GPIO_CTL_HI_REG;
mask = 1 << (gpio - 32);
}
spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
tmp = bcm_gpio_readl(reg);
if (dir == GPIO_DIR_IN)
tmp &= ~mask;
else
tmp |= mask;
bcm_gpio_writel(tmp, reg);
spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
return 0;
}
static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN);
}
static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
bcm63xx_gpio_set(chip, gpio, value);
return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT);
}
static struct gpio_chip bcm63xx_gpio_chip = {
.label = "bcm63xx-gpio",
.direction_input = bcm63xx_gpio_direction_input,
.direction_output = bcm63xx_gpio_direction_output,
.get = bcm63xx_gpio_get,
.set = bcm63xx_gpio_set,
.base = 0,
};
int __init bcm63xx_gpio_init(void)
{
bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
return gpiochip_add(&bcm63xx_gpio_chip);
}
arch_initcall(bcm63xx_gpio_init);
arch/mips/bcm63xx/irq.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
#include <bcm63xx_irq.h>
/*
* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
* prioritize any interrupt relatively to another. the static counter
* will resume the loop where it ended the last time we left this
* function.
*/
static void bcm63xx_irq_dispatch_internal(void)
{
u32 pending;
static int i;
pending = bcm_perf_readl(PERF_IRQMASK_REG) &
bcm_perf_readl(PERF_IRQSTAT_REG);
if (!pending)
return ;
while (1) {
int to_call = i;
i = (i + 1) & 0x1f;
if (pending & (1 << to_call)) {
do_IRQ(to_call + IRQ_INTERNAL_BASE);
break;
}
}
}
asmlinkage void plat_irq_dispatch(void)
{
u32 cause;
do {
cause = read_c0_cause() & read_c0_status() & ST0_IM;
if (!cause)
break;
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP2)
bcm63xx_irq_dispatch_internal();
if (cause & CAUSEF_IP3)
do_IRQ(IRQ_EXT_0);
if (cause & CAUSEF_IP4)
do_IRQ(IRQ_EXT_1);
if (cause & CAUSEF_IP5)
do_IRQ(IRQ_EXT_2);
if (cause & CAUSEF_IP6)
do_IRQ(IRQ_EXT_3);
} while (1);
}
/*
* internal IRQs operations: only mask/unmask on PERF irq mask
* register.
*/
static inline void bcm63xx_internal_irq_mask(unsigned int irq)
{
u32 mask;
irq -= IRQ_INTERNAL_BASE;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask &= ~(1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
}
static void bcm63xx_internal_irq_unmask(unsigned int irq)
{
u32 mask;
irq -= IRQ_INTERNAL_BASE;
mask = bcm_perf_readl(PERF_IRQMASK_REG);
mask |= (1 << irq);
bcm_perf_writel(mask, PERF_IRQMASK_REG);
}
static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
{
bcm63xx_internal_irq_unmask(irq);
return 0;
}
/*
* external IRQs operations: mask/unmask and clear on PERF external
* irq control register.
*/
static void bcm63xx_external_irq_mask(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static void bcm63xx_external_irq_unmask(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_MASK(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static void bcm63xx_external_irq_clear(unsigned int irq)
{
u32 reg;
irq -= IRQ_EXT_BASE;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg |= EXTIRQ_CFG_CLEAR(irq);
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
}
static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
{
set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
irq_enable_hazard();
bcm63xx_external_irq_unmask(irq);
return 0;
}
static void bcm63xx_external_irq_shutdown(unsigned int irq)
{
bcm63xx_external_irq_mask(irq);
clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
irq_disable_hazard();
}
static int bcm63xx_external_irq_set_type(unsigned int irq,
unsigned int flow_type)
{
u32 reg;
struct irq_desc *desc = irq_desc + irq;
irq -= IRQ_EXT_BASE;
flow_type &= IRQ_TYPE_SENSE_MASK;
if (flow_type == IRQ_TYPE_NONE)
flow_type = IRQ_TYPE_LEVEL_LOW;
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
switch (flow_type) {
case IRQ_TYPE_EDGE_BOTH:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_EDGE_RISING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_EDGE_FALLING:
reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg |= EXTIRQ_CFG_SENSE(irq);
break;
case IRQ_TYPE_LEVEL_LOW:
reg |= EXTIRQ_CFG_LEVELSENSE(irq);
reg &= ~EXTIRQ_CFG_SENSE(irq);
break;
default:
printk(KERN_ERR "bogus flow type combination given !\n");
return -EINVAL;
}
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
desc->status |= IRQ_LEVEL;
desc->handle_irq = handle_level_irq;
} else {
desc->handle_irq = handle_edge_irq;
}
return 0;
}
static struct irq_chip bcm63xx_internal_irq_chip = {
.name = "bcm63xx_ipic",
.startup = bcm63xx_internal_irq_startup,
.shutdown = bcm63xx_internal_irq_mask,
.mask = bcm63xx_internal_irq_mask,
.mask_ack = bcm63xx_internal_irq_mask,
.unmask = bcm63xx_internal_irq_unmask,
};
static struct irq_chip bcm63xx_external_irq_chip = {
.name = "bcm63xx_epic",
.startup = bcm63xx_external_irq_startup,
.shutdown = bcm63xx_external_irq_shutdown,
.ack = bcm63xx_external_irq_clear,
.mask = bcm63xx_external_irq_mask,
.unmask = bcm63xx_external_irq_unmask,
.set_type = bcm63xx_external_irq_set_type,
};
static struct irqaction cpu_ip2_cascade_action = {
.handler = no_action,
.name = "cascade_ip2",
};
void __init arch_init_irq(void)
{
int i;
mips_cpu_irq_init();
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
handle_level_irq);
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
handle_edge_irq);
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
}
arch/mips/bcm63xx/prom.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_gpio.h>
void __init prom_init(void)
{
u32 reg, mask;
bcm63xx_cpu_init();
/* stop any running watchdog */
bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
/* disable all hardware blocks clock for now */
if (BCMCPU_IS_6338())
mask = CKCTL_6338_ALL_SAFE_EN;
else if (BCMCPU_IS_6345())
mask = CKCTL_6345_ALL_SAFE_EN;
else if (BCMCPU_IS_6348())
mask = CKCTL_6348_ALL_SAFE_EN;
else
/* BCMCPU_IS_6358() */
mask = CKCTL_6358_ALL_SAFE_EN;
reg = bcm_perf_readl(PERF_CKCTL_REG);
reg &= ~mask;
bcm_perf_writel(reg, PERF_CKCTL_REG);
/* assign command line from kernel config */
strcpy(arcs_cmdline, CONFIG_CMDLINE);
/* register gpiochip */
bcm63xx_gpio_init();
/* do low level board init */
board_prom_init();
}
void __init prom_free_prom_memory(void)
{
}
arch/mips/bcm63xx/setup.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/ioport.h>
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/cacheflush.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_io.h>
void bcm63xx_machine_halt(void)
{
printk(KERN_INFO "System halted\n");
while (1)
;
}
static void bcm6348_a1_reboot(void)
{
u32 reg;
/* soft reset all blocks */
printk(KERN_INFO "soft-reseting all blocks ...\n");
reg = bcm_perf_readl(PERF_SOFTRESET_REG);
reg &= ~SOFTRESET_6348_ALL;
bcm_perf_writel(reg, PERF_SOFTRESET_REG);
mdelay(10);
reg = bcm_perf_readl(PERF_SOFTRESET_REG);
reg |= SOFTRESET_6348_ALL;
bcm_perf_writel(reg, PERF_SOFTRESET_REG);
mdelay(10);
/* Jump to the power on address. */
printk(KERN_INFO "jumping to reset vector.\n");
/* set high vectors (base at 0xbfc00000 */
set_c0_status(ST0_BEV | ST0_ERL);
/* run uncached in kseg0 */
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
__flush_cache_all();
/* remove all wired TLB entries */
write_c0_wired(0);
__asm__ __volatile__(
"jr\t%0"
:
: "r" (0xbfc00000));
while (1)
;
}
void bcm63xx_machine_reboot(void)
{
u32 reg;
/* mask and clear all external irq */
reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
reg &= ~EXTIRQ_CFG_MASK_ALL;
reg |= EXTIRQ_CFG_CLEAR_ALL;
bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
bcm6348_a1_reboot();
printk(KERN_INFO "triggering watchdog soft-reset...\n");
bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
while (1)
;
}
static void __bcm63xx_machine_reboot(char *p)
{
bcm63xx_machine_reboot();
}
/*
* return system type in /proc/cpuinfo
*/
const char *get_system_type(void)
{
static char buf[128];
snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)",
board_get_name(),
bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
return buf;
}
void __init plat_time_init(void)
{
mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
}
void __init plat_mem_setup(void)
{
add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
_machine_halt = bcm63xx_machine_halt;
_machine_restart = __bcm63xx_machine_reboot;
pm_power_off = bcm63xx_machine_halt;
set_io_port_base(0);
ioport_resource.start = 0;
ioport_resource.end = ~0;
board_setup();
}
int __init bcm63xx_register_devices(void)
{
return board_register_devices();
}
arch_initcall(bcm63xx_register_devices);
arch/mips/bcm63xx/timer.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_timer.h>
#include <bcm63xx_regs.h>
static DEFINE_SPINLOCK(timer_reg_lock);
static DEFINE_SPINLOCK(timer_data_lock);
static struct clk *periph_clk;
static struct timer_data {
void (*cb)(void *);
void *data;
} timer_data[BCM63XX_TIMER_COUNT];
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
u32 stat;
int i;
spin_lock(&timer_reg_lock);
stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
spin_unlock(&timer_reg_lock);
for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
continue;
spin_lock(&timer_data_lock);
if (!timer_data[i].cb) {
spin_unlock(&timer_data_lock);
continue;
}
timer_data[i].cb(timer_data[i].data);
spin_unlock(&timer_data_lock);
}
return IRQ_HANDLED;
}
int bcm63xx_timer_enable(int id)
{
u32 reg;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
reg |= TIMER_CTL_ENABLE_MASK;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_enable);
int bcm63xx_timer_disable(int id)
{
u32 reg;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
reg &= ~TIMER_CTL_ENABLE_MASK;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_disable);
int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
{
unsigned long flags;
int ret;
if (id >= BCM63XX_TIMER_COUNT || !callback)
return -EINVAL;
ret = 0;
spin_lock_irqsave(&timer_data_lock, flags);
if (timer_data[id].cb) {
ret = -EBUSY;
goto out;
}
timer_data[id].cb = callback;
timer_data[id].data = data;
out:
spin_unlock_irqrestore(&timer_data_lock, flags);
return ret;
}
EXPORT_SYMBOL(bcm63xx_timer_register);
void bcm63xx_timer_unregister(int id)
{
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return;
spin_lock_irqsave(&timer_data_lock, flags);
timer_data[id].cb = NULL;
spin_unlock_irqrestore(&timer_data_lock, flags);
}
EXPORT_SYMBOL(bcm63xx_timer_unregister);
unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
{
return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
}
EXPORT_SYMBOL(bcm63xx_timer_countdown);
int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
{
u32 reg, countdown;
unsigned long flags;
if (id >= BCM63XX_TIMER_COUNT)
return -EINVAL;
countdown = bcm63xx_timer_countdown(countdown_us);
if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
return -EINVAL;
spin_lock_irqsave(&timer_reg_lock, flags);
reg = bcm_timer_readl(TIMER_CTLx_REG(id));
if (monotonic)
reg &= ~TIMER_CTL_MONOTONIC_MASK;
else
reg |= TIMER_CTL_MONOTONIC_MASK;
reg &= ~TIMER_CTL_COUNTDOWN_MASK;
reg |= countdown;
bcm_timer_writel(reg, TIMER_CTLx_REG(id));
spin_unlock_irqrestore(&timer_reg_lock, flags);
return 0;
}
EXPORT_SYMBOL(bcm63xx_timer_set);
int bcm63xx_timer_init(void)
{
int ret, irq;
u32 reg;
reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
periph_clk = clk_get(NULL, "periph");
if (IS_ERR(periph_clk))
return -ENODEV;
irq = bcm63xx_get_irq_number(IRQ_TIMER);
ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
if (ret) {
printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
return ret;
}
return 0;
}
arch_initcall(bcm63xx_timer_init);
arch/mips/boot/elf2ecoff.c
View file @ 3dc95666
......@@ -59,8 +59,8 @@ struct sect {
};
int *symTypeTable;
int must_convert_endian = 0;
int format_bigendian = 0;
int must_convert_endian;
int format_bigendian;
static void copy(int out, int in, off_t offset, off_t size)
{
......
arch/mips/cavium-octeon/Makefile
View file @ 3dc95666
......@@ -6,10 +6,10 @@
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Copyright (C) 2005-2008 Cavium Networks
# Copyright (C) 2005-2009 Cavium Networks
#
obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
obj-y += dma-octeon.o flash_setup.o
obj-y += octeon-memcpy.o
......
arch/mips/cavium-octeon/octeon-platform.c 0 → 100644
View file @ 3dc95666
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004-2009 Cavium Networks
* Copyright (C) 2008 Wind River Systems
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-rnm-defs.h>
static struct octeon_cf_data octeon_cf_data;
static int __init octeon_cf_device_init(void)
{
union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
unsigned long base_ptr, region_base, region_size;
struct platform_device *pd;
struct resource cf_resources[3];
unsigned int num_resources;
int i;
int ret = 0;
/* Setup octeon-cf platform device if present. */
base_ptr = 0;
if (octeon_bootinfo->major_version == 1
&& octeon_bootinfo->minor_version >= 1) {
if (octeon_bootinfo->compact_flash_common_base_addr)
base_ptr =
octeon_bootinfo->compact_flash_common_base_addr;
} else {
base_ptr = 0x1d000800;
}
if (!base_ptr)
return ret;
/* Find CS0 region. */
for (i = 0; i < 8; i++) {
mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
region_base = mio_boot_reg_cfg.s.base << 16;
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
&& base_ptr < region_base + region_size)
break;
}
if (i >= 7) {
/* i and i + 1 are CS0 and CS1, both must be less than 8. */
goto out;
}
octeon_cf_data.base_region = i;
octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
octeon_cf_data.base_region_bias = base_ptr - region_base;
memset(cf_resources, 0, sizeof(cf_resources));
num_resources = 0;
cf_resources[num_resources].flags = IORESOURCE_MEM;
cf_resources[num_resources].start = region_base;
cf_resources[num_resources].end = region_base + region_size - 1;
num_resources++;
if (!(base_ptr & 0xfffful)) {
/*
* Boot loader signals availability of DMA (true_ide
* mode) by setting low order bits of base_ptr to
* zero.
*/
/* Asume that CS1 immediately follows. */
mio_boot_reg_cfg.u64 =
cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
region_base = mio_boot_reg_cfg.s.base << 16;
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
if (!mio_boot_reg_cfg.s.en)
goto out;
cf_resources[num_resources].flags = IORESOURCE_MEM;
cf_resources[num_resources].start = region_base;
cf_resources[num_resources].end = region_base + region_size - 1;
num_resources++;
octeon_cf_data.dma_engine = 0;
cf_resources[num_resources].flags = IORESOURCE_IRQ;
cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
num_resources++;
} else {
octeon_cf_data.dma_engine = -1;
}
pd = platform_device_alloc("pata_octeon_cf", -1);
if (!pd) {
ret = -ENOMEM;
goto out;
}
pd->dev.platform_data = &octeon_cf_data;
ret = platform_device_add_resources(pd, cf_resources, num_resources);
if (ret)
goto fail;
ret = platform_device_add(pd);
if (ret)
goto fail;
return ret;
fail:
platform_device_put(pd);
out:
return ret;
}
device_initcall(octeon_cf_device_init);
/* Octeon Random Number Generator. */
static int __init octeon_rng_device_init(void)
{
struct platform_device *pd;
int ret = 0;
struct resource rng_resources[] = {
{
.flags = IORESOURCE_MEM,
.start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
.end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
}, {
.flags = IORESOURCE_MEM,
.start = cvmx_build_io_address(8, 0),
.end = cvmx_build_io_address(8, 0) + 0x7
}
};
pd = platform_device_alloc("octeon_rng", -1);
if (!pd) {
ret = -ENOMEM;
goto out;
}
ret = platform_device_add_resources(pd, rng_resources,
ARRAY_SIZE(rng_resources));
if (ret)
goto fail;
ret = platform_device_add(pd);
if (ret)
goto fail;
return ret;
fail:
platform_device_put(pd);
out:
return ret;
}
device_initcall(octeon_rng_device_init);
MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Platform driver for Octeon SOC");
arch/mips/cavium-octeon/setup.c
View file @ 3dc95666
......@@ -11,7 +11,6 @@
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/serial.h>
#include <linux/smp.h>
#include <linux/types.h>
......@@ -824,105 +823,3 @@ void prom_free_prom_memory(void)
CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
octeon_hal_setup_reserved32();
}
static struct octeon_cf_data octeon_cf_data;
static int __init octeon_cf_device_init(void)
{
union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
unsigned long base_ptr, region_base, region_size;
struct platform_device *pd;
struct resource cf_resources[3];
unsigned int num_resources;
int i;
int ret = 0;
/* Setup octeon-cf platform device if present. */
base_ptr = 0;
if (octeon_bootinfo->major_version == 1
&& octeon_bootinfo->minor_version >= 1) {
if (octeon_bootinfo->compact_flash_common_base_addr)
base_ptr =
octeon_bootinfo->compact_flash_common_base_addr;
} else {
base_ptr = 0x1d000800;
}
if (!base_ptr)
return ret;
/* Find CS0 region. */
for (i = 0; i < 8; i++) {
mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
region_base = mio_boot_reg_cfg.s.base << 16;
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
&& base_ptr < region_base + region_size)
break;
}
if (i >= 7) {
/* i and i + 1 are CS0 and CS1, both must be less than 8. */
goto out;
}
octeon_cf_data.base_region = i;
octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
octeon_cf_data.base_region_bias = base_ptr - region_base;
memset(cf_resources, 0, sizeof(cf_resources));
num_resources = 0;
cf_resources[num_resources].flags = IORESOURCE_MEM;
cf_resources[num_resources].start = region_base;
cf_resources[num_resources].end = region_base + region_size - 1;
num_resources++;
if (!(base_ptr & 0xfffful)) {
/*
* Boot loader signals availability of DMA (true_ide
* mode) by setting low order bits of base_ptr to
* zero.
*/
/* Asume that CS1 immediately follows. */
mio_boot_reg_cfg.u64 =
cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
region_base = mio_boot_reg_cfg.s.base << 16;
region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
if (!mio_boot_reg_cfg.s.en)
goto out;
cf_resources[num_resources].flags = IORESOURCE_MEM;
cf_resources[num_resources].start = region_base;
cf_resources[num_resources].end = region_base + region_size - 1;
num_resources++;
octeon_cf_data.dma_engine = 0;
cf_resources[num_resources].flags = IORESOURCE_IRQ;
cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
num_resources++;
} else {
octeon_cf_data.dma_engine = -1;
}
pd = platform_device_alloc("pata_octeon_cf", -1);
if (!pd) {
ret = -ENOMEM;
goto out;
}
pd->dev.platform_data = &octeon_cf_data;
ret = platform_device_add_resources(pd, cf_resources, num_resources);
if (ret)
goto fail;
ret = platform_device_add(pd);
if (ret)
goto fail;
return ret;
fail:
platform_device_put(pd);
out:
return ret;
}
device_initcall(octeon_cf_device_init);
arch/mips/configs/ar7_defconfig
View file @ 3dc95666
......@@ -125,7 +125,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/bcm47xx_defconfig
View file @ 3dc95666
......@@ -111,7 +111,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/bcm63xx_defconfig 0 → 100644
View file @ 3dc95666
This diff is collapsed.
arch/mips/configs/bigsur_defconfig
View file @ 3dc95666
......@@ -129,7 +129,6 @@ CONFIG_PAGE_SIZE_4KB=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/cobalt_defconfig
View file @ 3dc95666
......@@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/db1000_defconfig
View file @ 3dc95666
......@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/db1100_defconfig
View file @ 3dc95666
......@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/db1200_defconfig
View file @ 3dc95666
......@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/db1500_defconfig
View file @ 3dc95666
......@@ -116,7 +116,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/db1550_defconfig
View file @ 3dc95666
......@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/excite_defconfig
View file @ 3dc95666
......@@ -118,7 +118,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/ip22_defconfig
View file @ 3dc95666
......@@ -130,7 +130,6 @@ CONFIG_IP22_CPU_SCACHE=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/ip27_defconfig
View file @ 3dc95666
......@@ -105,7 +105,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/ip28_defconfig
View file @ 3dc95666
......@@ -123,7 +123,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/ip32_defconfig
View file @ 3dc95666
......@@ -118,7 +118,6 @@ CONFIG_RM7000_CPU_SCACHE=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/jazz_defconfig
View file @ 3dc95666
......@@ -119,7 +119,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/lasat_defconfig
View file @ 3dc95666
......@@ -108,7 +108,6 @@ CONFIG_R5000_CPU_SCACHE=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/malta_defconfig
View file @ 3dc95666
......@@ -139,7 +139,6 @@ CONFIG_SYS_SUPPORTS_SCHED_SMT=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_MIPS_MT_FPAFF=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_CPU_HAS_LLSC=y
# CONFIG_CPU_HAS_SMARTMIPS is not set
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_MIPSR2_IRQ_EI=y
......
arch/mips/configs/markeins_defconfig
View file @ 3dc95666
......@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/mipssim_defconfig
View file @ 3dc95666
......@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/msp71xx_defconfig
View file @ 3dc95666
......@@ -129,7 +129,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/mtx1_defconfig
View file @ 3dc95666
......@@ -116,7 +116,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pb1100_defconfig
View file @ 3dc95666
......@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pb1500_defconfig
View file @ 3dc95666
......@@ -114,7 +114,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pb1550_defconfig
View file @ 3dc95666
......@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_64BIT_PHYS_ADDR=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pnx8335-stb225_defconfig
View file @ 3dc95666
......@@ -112,7 +112,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
......
arch/mips/configs/pnx8550-jbs_defconfig
View file @ 3dc95666
......@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pnx8550-stb810_defconfig
View file @ 3dc95666
......@@ -112,7 +112,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/rb532_defconfig
View file @ 3dc95666
......@@ -113,7 +113,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/rbtx49xx_defconfig
View file @ 3dc95666
......@@ -142,7 +142,6 @@ CONFIG_CPU_HAS_PREFETCH=y
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/rm200_defconfig
View file @ 3dc95666
......@@ -124,7 +124,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/sb1250-swarm_defconfig
View file @ 3dc95666
......@@ -133,7 +133,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
CONFIG_SB1_PASS_2_WORKAROUNDS=y
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/wrppmc_defconfig
View file @ 3dc95666
......@@ -120,7 +120,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/yosemite_defconfig
View file @ 3dc95666
......@@ -115,7 +115,6 @@ CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_VPE_LOADER is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/dec/prom/memory.c
View file @ 3dc95666
......@@ -18,7 +18,7 @@
#include <asm/sections.h>
volatile unsigned long mem_err = 0; /* So we know an error occurred */
volatile unsigned long mem_err; /* So we know an error occurred */
/*
* Probe memory in 4MB chunks, waiting for an error to tell us we've fallen
......
arch/mips/emma/markeins/setup.c
View file @ 3dc95666
......@@ -32,7 +32,7 @@
extern void markeins_led(const char *);
static int bus_frequency = 0;
static int bus_frequency;
static void markeins_machine_restart(char *command)
{
......
arch/mips/fw/arc/Makefile
View file @ 3dc95666
......@@ -8,3 +8,5 @@ lib-y += cmdline.o env.o file.o identify.o init.o \
lib-$(CONFIG_ARC_MEMORY) += memory.o
lib-$(CONFIG_ARC_CONSOLE) += arc_con.o
lib-$(CONFIG_ARC_PROMLIB) += promlib.o
EXTRA_CFLAGS += -Werror
arch/mips/fw/cfe/cfe_api.c
View file @ 3dc95666
......@@ -45,8 +45,8 @@ int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
* passed in two registers each, and CFE expects one.
*/
static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0;
static u64 cfe_handle = 0;
static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb);
static u64 cfe_handle;
int cfe_init(u64 handle, u64 ept)
{
......
arch/mips/include/asm/atomic.h
View file @ 3dc95666
......@@ -49,7 +49,7 @@
*/
static __inline__ void atomic_add(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
......@@ -61,7 +61,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
" .set mips0 \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
......@@ -94,7 +94,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
*/
static __inline__ void atomic_sub(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
......@@ -106,7 +106,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
" .set mips0 \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
......@@ -139,7 +139,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
......@@ -153,7 +153,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
......@@ -191,7 +191,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
......@@ -205,7 +205,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
......@@ -251,7 +251,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
int temp;
__asm__ __volatile__(
......@@ -269,7 +269,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
int temp;
__asm__ __volatile__(
......@@ -428,7 +428,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
*/
static __inline__ void atomic64_add(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
......@@ -440,7 +440,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
" .set mips0 \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
......@@ -473,7 +473,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
*/
static __inline__ void atomic64_sub(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
......@@ -485,7 +485,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
" .set mips0 \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
......@@ -518,7 +518,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
......@@ -532,7 +532,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
......@@ -570,7 +570,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
......@@ -584,7 +584,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
......@@ -630,7 +630,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
long temp;
__asm__ __volatile__(
......@@ -648,7 +648,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
long temp;
__asm__ __volatile__(
......
arch/mips/include/asm/bitops.h
View file @ 3dc95666
......@@ -61,7 +61,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
unsigned short bit = nr & SZLONG_MASK;
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
" .set mips3 \n"
"1: " __LL "%0, %1 # set_bit \n"
......@@ -72,7 +72,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << bit), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
} else if (__builtin_constant_p(bit)) {
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # set_bit \n"
" " __INS "%0, %4, %2, 1 \n"
......@@ -84,7 +84,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
: "=&r" (temp), "=m" (*m)
: "ir" (bit), "m" (*m), "r" (~0));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
__asm__ __volatile__(
" .set mips3 \n"
"1: " __LL "%0, %1 # set_bit \n"
......@@ -126,7 +126,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
unsigned short bit = nr & SZLONG_MASK;
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
" .set mips3 \n"
"1: " __LL "%0, %1 # clear_bit \n"
......@@ -137,7 +137,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
: "=&r" (temp), "=m" (*m)
: "ir" (~(1UL << bit)), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
} else if (__builtin_constant_p(bit)) {
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # clear_bit \n"
" " __INS "%0, $0, %2, 1 \n"
......@@ -149,7 +149,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
: "=&r" (temp), "=m" (*m)
: "ir" (bit), "m" (*m));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
__asm__ __volatile__(
" .set mips3 \n"
"1: " __LL "%0, %1 # clear_bit \n"
......@@ -202,7 +202,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned short bit = nr & SZLONG_MASK;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -215,7 +215,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << bit), "m" (*m));
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -260,7 +260,7 @@ static inline int test_and_set_bit(unsigned long nr,
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -275,7 +275,7 @@ static inline int test_and_set_bit(unsigned long nr,
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << bit), "m" (*m)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -328,7 +328,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
unsigned short bit = nr & SZLONG_MASK;
unsigned long res;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -343,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << bit), "m" (*m)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -397,7 +397,7 @@ static inline int test_and_clear_bit(unsigned long nr,
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -414,7 +414,7 @@ static inline int test_and_clear_bit(unsigned long nr,
: "r" (1UL << bit), "m" (*m)
: "memory");
#ifdef CONFIG_CPU_MIPSR2
} else if (__builtin_constant_p(nr)) {
} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -431,7 +431,7 @@ static inline int test_and_clear_bit(unsigned long nr,
: "ir" (bit), "m" (*m)
: "memory");
#endif
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -487,7 +487,7 @@ static inline int test_and_change_bit(unsigned long nr,
smp_llsc_mb();
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......@@ -502,7 +502,7 @@ static inline int test_and_change_bit(unsigned long nr,
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << bit), "m" (*m)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
......
arch/mips/include/asm/bootinfo.h
View file @ 3dc95666
......@@ -7,6 +7,7 @@
* Copyright (C) 1995, 1996 Andreas Busse
* Copyright (C) 1995, 1996 Stoned Elipot
* Copyright (C) 1995, 1996 Paul M. Antoine.
* Copyright (C) 2009 Zhang Le
*/
#ifndef _ASM_BOOTINFO_H
#define _ASM_BOOTINFO_H
......@@ -57,6 +58,17 @@
#define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */
#define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */
/*
* Valid machtype for Loongson family
*/
#define MACH_LOONGSON_UNKNOWN 0
#define MACH_LEMOTE_FL2E 1
#define MACH_LEMOTE_FL2F 2
#define MACH_LEMOTE_ML2F7 3
#define MACH_LEMOTE_YL2F89 4
#define MACH_DEXXON_GDIUM2F10 5
#define MACH_LOONGSON_END 6
#define CL_SIZE COMMAND_LINE_SIZE
extern char *system_type;
......
arch/mips/include/asm/cmpxchg.h
View file @ 3dc95666
......@@ -16,7 +16,7 @@
({ \
__typeof(*(m)) __ret; \
\
if (cpu_has_llsc && R10000_LLSC_WAR) { \
if (kernel_uses_llsc && R10000_LLSC_WAR) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
......@@ -33,7 +33,7 @@
: "=&r" (__ret), "=R" (*m) \
: "R" (*m), "Jr" (old), "Jr" (new) \
: "memory"); \
} else if (cpu_has_llsc) { \
} else if (kernel_uses_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
......
arch/mips/include/asm/cpu-features.h
View file @ 3dc95666
......@@ -80,6 +80,9 @@
#ifndef cpu_has_llsc
#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
......
arch/mips/include/asm/cpu.h
View file @ 3dc95666
......@@ -113,6 +113,12 @@
#define PRID_IMP_BCM4710 0x4000
#define PRID_IMP_BCM3302 0x9000
#define PRID_IMP_BCM6338 0x9000
#define PRID_IMP_BCM6345 0x8000
#define PRID_IMP_BCM6348 0x9100
#define PRID_IMP_BCM4350 0xA000
#define PRID_REV_BCM6358 0x0010
#define PRID_REV_BCM6368 0x0030
/*
* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
......@@ -210,6 +216,7 @@ enum cpu_type_enum {
*/
CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
/*
* MIPS64 class processors
......
arch/mips/include/asm/delay.h
View file @ 3dc95666
......@@ -11,6 +11,8 @@
#ifndef _ASM_DELAY_H
#define _ASM_DELAY_H
#include <linux/param.h>
extern void __delay(unsigned int loops);
extern void __ndelay(unsigned int ns);
extern void __udelay(unsigned int us);
......
arch/mips/include/asm/fixmap.h
View file @ 3dc95666
......@@ -67,11 +67,15 @@ enum fixed_addresses {
* the start of the fixmap, and leave one page empty
* at the top of mem..
*/
#ifdef CONFIG_BCM63XX
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
#else
#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
#define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000))
#else
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
#endif
#endif
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
......
arch/mips/include/asm/hardirq.h
View file @ 3dc95666
......@@ -10,15 +10,9 @@
#ifndef _ASM_HARDIRQ_H
#define _ASM_HARDIRQ_H
#include <linux/threads.h>
#include <linux/irq.h>
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
extern void ack_bad_irq(unsigned int irq);
#define ack_bad_irq ack_bad_irq
#include <asm-generic/hardirq.h>
#endif /* _ASM_HARDIRQ_H */
arch/mips/include/asm/lasat/lasat.h
View file @ 3dc95666
......@@ -227,6 +227,7 @@ extern void lasat_write_eeprom_info(void);
* It is used for the bit-banging rtc and eeprom drivers */
#include <linux/delay.h>
#include <linux/smp.h>
/* calculating with the slowest board with 100 MHz clock */
#define LASAT_100_DIVIDER 20
......
arch/mips/include/asm/local.h
View file @ 3dc95666
......@@ -29,7 +29,7 @@ static __inline__ long local_add_return(long i, local_t * l)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
......@@ -43,7 +43,7 @@ static __inline__ long local_add_return(long i, local_t * l)
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
......@@ -74,7 +74,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
......@@ -88,7 +88,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
: "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
: "Ir" (i), "m" (l->a.counter)
: "memory");
} else if (cpu_has_llsc) {
} else if (kernel_uses_llsc) {
unsigned long temp;
__asm__ __volatile__(
......
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
View file @ 3dc95666
......@@ -578,6 +578,15 @@ static inline int irq_to_gpio(int irq)
return alchemy_irq_to_gpio(irq);
}
static inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
static inline void gpio_free(unsigned gpio)
{
}
#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
......
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