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Commit 3e26186d authored by Shannon Nelson's avatar Shannon Nelson Committed by Jeff Kirsher
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i40e: clean up comment style 

Lots of trivial changes to remove double spaces in function headers,
unnecessary periods in short comments, and adjust the English usage here
and there.

No actual code was harmed in the making of this patch.

Change-ID: I6e756c500756945e81a61ffb10221753eb7923ea
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Acked-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: default avatarKevin Scott <kevin.c.scott@intel.com>
Signed-off-by: default avatarCatherine Sullivan <catherine.sullivan@intel.com>
Tested-by: default avatarKavindya Deegala <kavindya.s.deegala@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 206812b5
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Showing with 58 additions and 59 deletions
drivers/net/ethernet/intel/i40e/i40e_nvm.c
View file @ 3e26186d
...@@ -27,14 +27,14 @@ ...@@ -27,14 +27,14 @@
#include "i40e_prototype.h" #include "i40e_prototype.h"
/** /**
* i40e_init_nvm_ops - Initialize NVM function pointers. * i40e_init_nvm_ops - Initialize NVM function pointers
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* *
* Setups the function pointers and the NVM info structure. Should be called * Setup the function pointers and the NVM info structure. Should be called
* once per NVM initialization, e.g. inside the i40e_init_shared_code(). * once per NVM initialization, e.g. inside the i40e_init_shared_code().
* Please notice that the NVM term is used here (& in all methods covered * Please notice that the NVM term is used here (& in all methods covered
* in this file) as an equivalent of the FLASH part mapped into the SR. * in this file) as an equivalent of the FLASH part mapped into the SR.
* We are accessing FLASH always thru the Shadow RAM. * We are accessing FLASH always thru the Shadow RAM.
**/ **/
i40e_status i40e_init_nvm(struct i40e_hw *hw) i40e_status i40e_init_nvm(struct i40e_hw *hw)
{ {
...@@ -49,16 +49,16 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw) ...@@ -49,16 +49,16 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw)
gens = rd32(hw, I40E_GLNVM_GENS); gens = rd32(hw, I40E_GLNVM_GENS);
sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >> sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
I40E_GLNVM_GENS_SR_SIZE_SHIFT); I40E_GLNVM_GENS_SR_SIZE_SHIFT);
/* Switching to words (sr_size contains power of 2KB). */ /* Switching to words (sr_size contains power of 2KB) */
nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB; nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
/* Check if we are in the normal or blank NVM programming mode. */ /* Check if we are in the normal or blank NVM programming mode */
fla = rd32(hw, I40E_GLNVM_FLA); fla = rd32(hw, I40E_GLNVM_FLA);
if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode. */ if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
/* Max NVM timeout. */ /* Max NVM timeout */
nvm->timeout = I40E_MAX_NVM_TIMEOUT; nvm->timeout = I40E_MAX_NVM_TIMEOUT;
nvm->blank_nvm_mode = false; nvm->blank_nvm_mode = false;
} else { /* Blank programming mode. */ } else { /* Blank programming mode */
nvm->blank_nvm_mode = true; nvm->blank_nvm_mode = true;
ret_code = I40E_ERR_NVM_BLANK_MODE; ret_code = I40E_ERR_NVM_BLANK_MODE;
hw_dbg(hw, "NVM init error: unsupported blank mode.\n"); hw_dbg(hw, "NVM init error: unsupported blank mode.\n");
...@@ -68,12 +68,12 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw) ...@@ -68,12 +68,12 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw)
} }
/** /**
* i40e_acquire_nvm - Generic request for acquiring the NVM ownership. * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* @access: NVM access type (read or write). * @access: NVM access type (read or write)
* *
* This function will request NVM ownership for reading * This function will request NVM ownership for reading
* via the proper Admin Command. * via the proper Admin Command.
**/ **/
i40e_status i40e_acquire_nvm(struct i40e_hw *hw, i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
enum i40e_aq_resource_access_type access) enum i40e_aq_resource_access_type access)
...@@ -87,20 +87,20 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw, ...@@ -87,20 +87,20 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access, ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
0, &time, NULL); 0, &time, NULL);
/* Reading the Global Device Timer. */ /* Reading the Global Device Timer */
gtime = rd32(hw, I40E_GLVFGEN_TIMER); gtime = rd32(hw, I40E_GLVFGEN_TIMER);
/* Store the timeout. */ /* Store the timeout */
hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime; hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime;
if (ret_code) { if (ret_code) {
/* Set the polling timeout. */ /* Set the polling timeout */
if (time > I40E_MAX_NVM_TIMEOUT) if (time > I40E_MAX_NVM_TIMEOUT)
timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT)
+ gtime; + gtime;
else else
timeout = hw->nvm.hw_semaphore_timeout; timeout = hw->nvm.hw_semaphore_timeout;
/* Poll until the current NVM owner timeouts. */ /* Poll until the current NVM owner timeouts */
while (gtime < timeout) { while (gtime < timeout) {
usleep_range(10000, 20000); usleep_range(10000, 20000);
ret_code = i40e_aq_request_resource(hw, ret_code = i40e_aq_request_resource(hw,
...@@ -128,10 +128,10 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw, ...@@ -128,10 +128,10 @@ i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
} }
/** /**
* i40e_release_nvm - Generic request for releasing the NVM ownership. * i40e_release_nvm - Generic request for releasing the NVM ownership
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* *
* This function will release NVM resource via the proper Admin Command. * This function will release NVM resource via the proper Admin Command.
**/ **/
void i40e_release_nvm(struct i40e_hw *hw) void i40e_release_nvm(struct i40e_hw *hw)
{ {
...@@ -140,17 +140,17 @@ void i40e_release_nvm(struct i40e_hw *hw) ...@@ -140,17 +140,17 @@ void i40e_release_nvm(struct i40e_hw *hw)
} }
/** /**
* i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit. * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* *
* Polls the SRCTL Shadow RAM register done bit. * Polls the SRCTL Shadow RAM register done bit.
**/ **/
static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
{ {
i40e_status ret_code = I40E_ERR_TIMEOUT; i40e_status ret_code = I40E_ERR_TIMEOUT;
u32 srctl, wait_cnt; u32 srctl, wait_cnt;
/* Poll the I40E_GLNVM_SRCTL until the done bit is set. */ /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
srctl = rd32(hw, I40E_GLNVM_SRCTL); srctl = rd32(hw, I40E_GLNVM_SRCTL);
if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) { if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
...@@ -165,12 +165,12 @@ static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw) ...@@ -165,12 +165,12 @@ static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
} }
/** /**
* i40e_read_nvm_word - Reads Shadow RAM * i40e_read_nvm_word - Reads Shadow RAM
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
* @data: word read from the Shadow RAM. * @data: word read from the Shadow RAM
* *
* Reads 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
**/ **/
i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
u16 *data) u16 *data)
...@@ -184,15 +184,15 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, ...@@ -184,15 +184,15 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
goto read_nvm_exit; goto read_nvm_exit;
} }
/* Poll the done bit first. */ /* Poll the done bit first */
ret_code = i40e_poll_sr_srctl_done_bit(hw); ret_code = i40e_poll_sr_srctl_done_bit(hw);
if (!ret_code) { if (!ret_code) {
/* Write the address and start reading. */ /* Write the address and start reading */
sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) | sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
(1 << I40E_GLNVM_SRCTL_START_SHIFT); (1 << I40E_GLNVM_SRCTL_START_SHIFT);
wr32(hw, I40E_GLNVM_SRCTL, sr_reg); wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
/* Poll I40E_GLNVM_SRCTL until the done bit is set. */ /* Poll I40E_GLNVM_SRCTL until the done bit is set */
ret_code = i40e_poll_sr_srctl_done_bit(hw); ret_code = i40e_poll_sr_srctl_done_bit(hw);
if (!ret_code) { if (!ret_code) {
sr_reg = rd32(hw, I40E_GLNVM_SRDATA); sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
...@@ -210,16 +210,15 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, ...@@ -210,16 +210,15 @@ i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
} }
/** /**
* i40e_read_nvm_buffer - Reads Shadow RAM buffer. * i40e_read_nvm_buffer - Reads Shadow RAM buffer
* @hw: pointer to the HW structure. * @hw: pointer to the HW structure
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
* @words: number of words to read (in) & * @words: (in) number of words to read; (out) number of words actually read
* number of words read before the NVM ownership timeout (out). * @data: words read from the Shadow RAM
* @data: words read from the Shadow RAM.
* *
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
* method. The buffer read is preceded by the NVM ownership take * method. The buffer read is preceded by the NVM ownership take
* and followed by the release. * and followed by the release.
**/ **/
i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
u16 *words, u16 *data) u16 *words, u16 *data)
...@@ -227,7 +226,7 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, ...@@ -227,7 +226,7 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
i40e_status ret_code = 0; i40e_status ret_code = 0;
u16 index, word; u16 index, word;
/* Loop thru the selected region. */ /* Loop thru the selected region */
for (word = 0; word < *words; word++) { for (word = 0; word < *words; word++) {
index = offset + word; index = offset + word;
ret_code = i40e_read_nvm_word(hw, index, &data[word]); ret_code = i40e_read_nvm_word(hw, index, &data[word]);
...@@ -235,21 +234,21 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, ...@@ -235,21 +234,21 @@ i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
break; break;
} }
/* Update the number of words read from the Shadow RAM. */ /* Update the number of words read from the Shadow RAM */
*words = word; *words = word;
return ret_code; return ret_code;
} }
/** /**
* i40e_calc_nvm_checksum - Calculates and returns the checksum * i40e_calc_nvm_checksum - Calculates and returns the checksum
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @checksum: pointer to the checksum * @checksum: pointer to the checksum
* *
* This function calculate SW Checksum that covers the whole 64kB shadow RAM * This function calculates SW Checksum that covers the whole 64kB shadow RAM
* except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
* is customer specific and unknown. Therefore, this function skips all maximum * is customer specific and unknown. Therefore, this function skips all maximum
* possible size of VPD (1kB). * possible size of VPD (1kB).
**/ **/
static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
u16 *checksum) u16 *checksum)
...@@ -311,12 +310,12 @@ static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw, ...@@ -311,12 +310,12 @@ static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
} }
/** /**
* i40e_validate_nvm_checksum - Validate EEPROM checksum * i40e_validate_nvm_checksum - Validate EEPROM checksum
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* @checksum: calculated checksum * @checksum: calculated checksum
* *
* Performs checksum calculation and validates the NVM SW checksum. If the * Performs checksum calculation and validates the NVM SW checksum. If the
* caller does not need checksum, the value can be NULL. * caller does not need checksum, the value can be NULL.
**/ **/
i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw, i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
u16 *checksum) u16 *checksum)
......
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