Commit 3e5d0641 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson

drm/i915: Move i915_power_well_id out of i915_reg.h

It has nothing to do with registers, so move it to the more appropriate
intel_display_power.h
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190816012343.36433-2-daniele.ceraolospurio@intel.com
parent df403069
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include "intel_cdclk.h" #include "intel_cdclk.h"
#include "intel_combo_phy.h" #include "intel_combo_phy.h"
#include "intel_csr.h" #include "intel_csr.h"
#include "intel_display_power.h"
#include "intel_display_types.h" #include "intel_display_types.h"
#include "intel_dpio_phy.h" #include "intel_dpio_phy.h"
#include "intel_hotplug.h" #include "intel_hotplug.h"
......
...@@ -92,6 +92,27 @@ enum intel_display_power_domain { ...@@ -92,6 +92,27 @@ enum intel_display_power_domain {
POWER_DOMAIN_NUM, POWER_DOMAIN_NUM,
}; };
/*
* i915_power_well_id:
*
* IDs used to look up power wells. Power wells accessed directly bypassing
* the power domains framework must be assigned a unique ID. The rest of power
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
DISP_PW_ID_NONE,
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
VLV_DISP_PW_DPIO_CMN_BC,
GLK_DISP_PW_DPIO_CMN_C,
CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <drm/i915_component.h> #include <drm/i915_component.h>
#include "i915_reg.h" #include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h" #include "intel_display_types.h"
#include "intel_hdcp.h" #include "intel_hdcp.h"
#include "intel_sideband.h" #include "intel_sideband.h"
......
...@@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) ...@@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define PUNIT_REG_ISPSSPM0 0x39 #define PUNIT_REG_ISPSSPM0 0x39
#define PUNIT_REG_ISPSSPM1 0x3a #define PUNIT_REG_ISPSSPM1 0x3a
/*
* i915_power_well_id:
*
* IDs used to look up power wells. Power wells accessed directly bypassing
* the power domains framework must be assigned a unique ID. The rest of power
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
DISP_PW_ID_NONE,
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
VLV_DISP_PW_DPIO_CMN_BC,
GLK_DISP_PW_DPIO_CMN_C,
CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
};
#define PUNIT_REG_PWRGT_CTRL 0x60 #define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61 #define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
......
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