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Commit 3e67f4f2 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu/nv: convert to IP version checking 

Use IP versions rather than asic_type to differentiate
IP version specific features.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 96626a0e
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Inline Side-by-side
Showing with 38 additions and 37 deletions
drivers/gpu/drm/amd/amdgpu/nv.c
View file @ 3e67f4f2
...@@ -180,8 +180,8 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = { ...@@ -180,8 +180,8 @@ static const struct amdgpu_video_codecs yc_video_codecs_decode = {
static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
const struct amdgpu_video_codecs **codecs) const struct amdgpu_video_codecs **codecs)
{ {
switch (adev->asic_type) { switch (adev->ip_versions[UVD_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(3, 0, 0):
if (amdgpu_sriov_vf(adev)) { if (amdgpu_sriov_vf(adev)) {
if (encode) if (encode)
*codecs = &sriov_sc_video_codecs_encode; *codecs = &sriov_sc_video_codecs_encode;
...@@ -194,29 +194,27 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, ...@@ -194,29 +194,27 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
*codecs = &sc_video_codecs_decode; *codecs = &sc_video_codecs_decode;
} }
return 0; return 0;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(3, 0, 16):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(3, 0, 2):
case CHIP_VANGOGH:
if (encode) if (encode)
*codecs = &nv_video_codecs_encode; *codecs = &nv_video_codecs_encode;
else else
*codecs = &sc_video_codecs_decode; *codecs = &sc_video_codecs_decode;
return 0; return 0;
case CHIP_YELLOW_CARP: case IP_VERSION(3, 1, 1):
if (encode) if (encode)
*codecs = &nv_video_codecs_encode; *codecs = &nv_video_codecs_encode;
else else
*codecs = &yc_video_codecs_decode; *codecs = &yc_video_codecs_decode;
return 0; return 0;
case CHIP_BEIGE_GOBY: case IP_VERSION(3, 0, 33):
if (encode) if (encode)
*codecs = &bg_video_codecs_encode; *codecs = &bg_video_codecs_encode;
else else
*codecs = &bg_video_codecs_decode; *codecs = &bg_video_codecs_decode;
return 0; return 0;
case CHIP_NAVI10: case IP_VERSION(2, 0, 0):
case CHIP_NAVI14: case IP_VERSION(2, 0, 2):
case CHIP_NAVI12:
if (encode) if (encode)
*codecs = &nv_video_codecs_encode; *codecs = &nv_video_codecs_encode;
else else
...@@ -511,14 +509,15 @@ nv_asic_reset_method(struct amdgpu_device *adev) ...@@ -511,14 +509,15 @@ nv_asic_reset_method(struct amdgpu_device *adev)
dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
amdgpu_reset_method); amdgpu_reset_method);
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP]) {
case CHIP_VANGOGH: case IP_VERSION(11, 5, 0):
case CHIP_YELLOW_CARP: case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
return AMD_RESET_METHOD_MODE2; return AMD_RESET_METHOD_MODE2;
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
return AMD_RESET_METHOD_MODE1; return AMD_RESET_METHOD_MODE1;
default: default:
if (amdgpu_dpm_is_baco_supported(adev)) if (amdgpu_dpm_is_baco_supported(adev))
...@@ -1046,8 +1045,11 @@ static int nv_common_early_init(void *handle) ...@@ -1046,8 +1045,11 @@ static int nv_common_early_init(void *handle)
adev->rev_id = nv_get_rev_id(adev); adev->rev_id = nv_get_rev_id(adev);
adev->external_rev_id = 0xff; adev->external_rev_id = 0xff;
switch (adev->asic_type) { /* TODO: split the GC and PG flags based on the relevant IP version for which
case CHIP_NAVI10: * they are relevant.
*/
switch (adev->ip_versions[GC_HWIP]) {
case IP_VERSION(10, 1, 10):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_IH_CG |
...@@ -1069,7 +1071,7 @@ static int nv_common_early_init(void *handle) ...@@ -1069,7 +1071,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_ATHUB; AMD_PG_SUPPORT_ATHUB;
adev->external_rev_id = adev->rev_id + 0x1; adev->external_rev_id = adev->rev_id + 0x1;
break; break;
case CHIP_NAVI14: case IP_VERSION(10, 1, 1):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_IH_CG | AMD_CG_SUPPORT_IH_CG |
...@@ -1090,7 +1092,7 @@ static int nv_common_early_init(void *handle) ...@@ -1090,7 +1092,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_VCN_DPG; AMD_PG_SUPPORT_VCN_DPG;
adev->external_rev_id = adev->rev_id + 20; adev->external_rev_id = adev->rev_id + 20;
break; break;
case CHIP_NAVI12: case IP_VERSION(10, 1, 2):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
...@@ -1119,7 +1121,7 @@ static int nv_common_early_init(void *handle) ...@@ -1119,7 +1121,7 @@ static int nv_common_early_init(void *handle)
adev->rev_id = 0; adev->rev_id = 0;
adev->external_rev_id = adev->rev_id + 0xa; adev->external_rev_id = adev->rev_id + 0xa;
break; break;
case CHIP_SIENNA_CICHLID: case IP_VERSION(10, 3, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
...@@ -1143,7 +1145,7 @@ static int nv_common_early_init(void *handle) ...@@ -1143,7 +1145,7 @@ static int nv_common_early_init(void *handle)
} }
adev->external_rev_id = adev->rev_id + 0x28; adev->external_rev_id = adev->rev_id + 0x28;
break; break;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(10, 3, 2):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
...@@ -1162,8 +1164,7 @@ static int nv_common_early_init(void *handle) ...@@ -1162,8 +1164,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB; AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x32; adev->external_rev_id = adev->rev_id + 0x32;
break; break;
case IP_VERSION(10, 3, 1):
case CHIP_VANGOGH:
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CP_LS |
...@@ -1186,7 +1187,7 @@ static int nv_common_early_init(void *handle) ...@@ -1186,7 +1187,7 @@ static int nv_common_early_init(void *handle)
if (adev->apu_flags & AMD_APU_IS_VANGOGH) if (adev->apu_flags & AMD_APU_IS_VANGOGH)
adev->external_rev_id = adev->rev_id + 0x01; adev->external_rev_id = adev->rev_id + 0x01;
break; break;
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(10, 3, 4):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
...@@ -1205,7 +1206,7 @@ static int nv_common_early_init(void *handle) ...@@ -1205,7 +1206,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB; AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x3c; adev->external_rev_id = adev->rev_id + 0x3c;
break; break;
case CHIP_BEIGE_GOBY: case IP_VERSION(10, 3, 5):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
...@@ -1222,7 +1223,7 @@ static int nv_common_early_init(void *handle) ...@@ -1222,7 +1223,7 @@ static int nv_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB; AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x46; adev->external_rev_id = adev->rev_id + 0x46;
break; break;
case CHIP_YELLOW_CARP: case IP_VERSION(10, 3, 3):
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
...@@ -1251,7 +1252,7 @@ static int nv_common_early_init(void *handle) ...@@ -1251,7 +1252,7 @@ static int nv_common_early_init(void *handle)
else else
adev->external_rev_id = adev->rev_id + 0x01; adev->external_rev_id = adev->rev_id + 0x01;
break; break;
case CHIP_CYAN_SKILLFISH: case IP_VERSION(10, 1, 3):
adev->cg_flags = 0; adev->cg_flags = 0;
adev->pg_flags = 0; adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x82; adev->external_rev_id = adev->rev_id + 0x82;
...@@ -1378,14 +1379,14 @@ static int nv_common_set_clockgating_state(void *handle, ...@@ -1378,14 +1379,14 @@ static int nv_common_set_clockgating_state(void *handle,
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return 0; return 0;
switch (adev->asic_type) { switch (adev->ip_versions[NBIO_HWIP]) {
case CHIP_NAVI10: case IP_VERSION(2, 3, 0):
case CHIP_NAVI14: case IP_VERSION(2, 3, 1):
case CHIP_NAVI12: case IP_VERSION(2, 3, 2):
case CHIP_SIENNA_CICHLID: case IP_VERSION(3, 3, 0):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(3, 3, 1):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(3, 3, 2):
case CHIP_BEIGE_GOBY: case IP_VERSION(3, 3, 3):
adev->nbio.funcs->update_medium_grain_clock_gating(adev, adev->nbio.funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE); state == AMD_CG_STATE_GATE);
adev->nbio.funcs->update_medium_grain_light_sleep(adev, adev->nbio.funcs->update_medium_grain_light_sleep(adev,
......
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