Commit 3ec04c3a authored by Juerg Haefliger's avatar Juerg Haefliger Committed by Stefan Bader

UBUNTU: SAUCE: Rename osb() to barrier_nospec()

BugLink: https://bugs.launchpad.net/bugs/1774181

The x86 barrier macro that landed in upstream is named barrier_nospec()
and is an LFENCE/MFENCE alternative. What was added in Ubuntu with the
original embargoed patches is named osb() but it's the same thing, so
rename it.

Also, rename the Ubuntu-specific non-x86 osb() macros and simplify the
code to turn barrier_nospec() into a no-op for arches that don't support
it.

And while we're at it, drop the reporting of osb for x86. It's always
enabled and OSB is not a recognizable upstream term and only adds confusion.
Signed-off-by: default avatarJuerg Haefliger <juergh@canonical.com>
Acked-by: default avatarStefan Bader <stefan.bader@canonical.com>
Acked-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
Signed-off-by: default avatarStefan Bader <stefan.bader@canonical.com>
parent 0a4e8a3e
......@@ -59,8 +59,6 @@ extern void arm_heavy_mb(void);
#define dma_rmb() barrier()
#define dma_wmb() barrier()
#endif
#define osb() do { } while (0)
#define osb_is_enabled (0)
#ifndef CONFIG_SMP
#define smp_mb() barrier()
......
......@@ -31,8 +31,6 @@
#define mb() dsb(sy)
#define rmb() dsb(ld)
#define wmb() dsb(st)
#define osb() do { } while (0)
#define osb_is_enabled (0)
#define dma_rmb() dmb(oshld)
#define dma_wmb() dmb(oshst)
......
......@@ -36,7 +36,8 @@
#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); smp_mb(); } while (0)
#define osb() asm volatile("ori 31,31,0")
/* Prevent speculative execution past this barrier. */
#define barrier_nospec() asm volatile("ori 31,31,0")
/* The sub-arch has lwsync */
#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
......
......@@ -24,13 +24,12 @@
#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
static inline void osb(void)
{
asm volatile(
ALTERNATIVE("", ".long 0xb2e8f000", 81)
: : : "memory");
}
#define osb osb
/* Prevent speculative execution past this barrier. */
#define barrier_nospec() \
do { \
asm volatile(ALTERNATIVE("", ".long 0xb2e8f000", 81) \
: : : "memory"); \
} while (0)
#define rmb() barrier()
#define wmb() barrier()
......
......@@ -105,8 +105,6 @@ do { \
#endif
#define osb() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)
/* Atomic operations are already serializing on x86 */
#define __smp_mb__before_atomic() barrier()
#define __smp_mb__after_atomic() barrier()
......
......@@ -681,13 +681,6 @@ void x86_spec_ctrl_setup_ap(void)
#ifdef CONFIG_SYSFS
#ifndef osb
#define osb_is_enabled (0)
#endif
#ifndef osb_is_enabled
#define osb_is_enabled (1)
#endif
static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
char *buf, unsigned int bug)
{
......@@ -702,9 +695,7 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
break;
case X86_BUG_SPECTRE_V1:
return sprintf(buf, "Mitigation: __user pointer sanitization%s%s\n",
osb_is_enabled ? ", OSB (observable speculation barrier, Intel v6)" : "");
return sprintf(buf, "Mitigation: __user pointer sanitization\n");
break;
case X86_BUG_SPECTRE_V2:
......
......@@ -9,6 +9,10 @@
struct task_struct;
#ifndef barrier_nospec
#define barrier_nospec() do { } while (0)
#endif
/**
* array_index_mask_nospec() - generate a ~0 mask when index < size, 0 otherwise
* @index: array element index
......
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