Commit 3f2b5941 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'imx-fixes-5.5-2' of...

Merge tag 'imx-fixes-5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes

i.MX fixes for 5.5, round 2:

 - Fix i.MX8MM SDMA1 AHB clock setting to remove a "Timeout waiting for CH0"
   error seen with UART1.
 - Correct compatible of RV3029 RTC device on imx6q-dhcom board.
 - Correct interrupt trigger type for magnetometer on board
   imx8mq-librem5-devkit.
 - A series from Anson Huang to fix vdd3p0 power supplier for a few NXP
   development board.
 - Fix imx6q-icore-mipi board to use 1.5 version of i.Core MX6DL, so
   that Ethernet interface on the board works properly.
 - Fix Toradex Colibri board to get NAND flash support back.
 - Fix SGTL5000 VDDIO regulator connection for imx6q-dhcom, which
   is connected to PMIC SW2 output rather than a fixed 3V3 rail.
 - Fix 'reg' of CPU node on imx7ulp to get rid of a warning given by
   kernel.
 - Fix endian setting for DCFG on LS1028A SoC, so that register access
   of DCFG becomes correct.

* tag 'imx-fixes-5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx7: Fix Toradex Colibri iMX7S 256MB NAND flash support
  ARM: dts: imx6sll-evk: Remove incorrect power supply assignment
  ARM: dts: imx6sl-evk: Remove incorrect power supply assignment
  ARM: dts: imx6sx-sdb: Remove incorrect power supply assignment
  ARM: dts: imx6qdl-sabresd: Remove incorrect power supply assignment
  ARM: dts: imx6q-icore-mipi: Use 1.5 version of i.Core MX6DL
  arm64: dts: imx8mq-librem5-devkit: use correct interrupt for the magnetometer
  ARM: dts: imx6q-dhcom: Fix SGTL5000 VDDIO regulator connection
  ARM: dts: imx7ulp: fix reg of cpu node
  arm64: dts: imx8mm: Change SDMA1 ahb clock for imx8mm
  arm64: dts: ls1028a: fix endian setting for dcfg
  ARM: dts: imx6q-dhcom: fix rtc compatible

Link: https://lore.kernel.org/r/20200110011836.GW4456@T480Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents dc64f487 4b0b97e6
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
/dts-v1/; /dts-v1/;
#include "imx6dl.dtsi" #include "imx6dl.dtsi"
#include "imx6qdl-icore.dtsi" #include "imx6qdl-icore-1.5.dtsi"
/ { / {
model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit";
......
...@@ -63,7 +63,7 @@ sgtl5000: codec@a { ...@@ -63,7 +63,7 @@ sgtl5000: codec@a {
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
clocks = <&clk_ext_audio_codec>; clocks = <&clk_ext_audio_codec>;
VDDA-supply = <&reg_3p3v>; VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>; VDDIO-supply = <&sw2_reg>;
}; };
}; };
......
...@@ -204,7 +204,7 @@ eeprom@50 { ...@@ -204,7 +204,7 @@ eeprom@50 {
}; };
rtc@56 { rtc@56 {
compatible = "rv3029c2"; compatible = "microcrystal,rv3029";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_hw300>; pinctrl-0 = <&pinctrl_rtc_hw300>;
reg = <0x56>; reg = <0x56>;
......
...@@ -749,10 +749,6 @@ &reg_vdd1p1 { ...@@ -749,10 +749,6 @@ &reg_vdd1p1 {
vin-supply = <&vgen5_reg>; vin-supply = <&vgen5_reg>;
}; };
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 { &reg_vdd2p5 {
vin-supply = <&vgen5_reg>; vin-supply = <&vgen5_reg>;
}; };
......
...@@ -584,10 +584,6 @@ &reg_vdd1p1 { ...@@ -584,10 +584,6 @@ &reg_vdd1p1 {
vin-supply = <&sw2_reg>; vin-supply = <&sw2_reg>;
}; };
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 { &reg_vdd2p5 {
vin-supply = <&sw2_reg>; vin-supply = <&sw2_reg>;
}; };
......
...@@ -265,10 +265,6 @@ &pwm1 { ...@@ -265,10 +265,6 @@ &pwm1 {
status = "okay"; status = "okay";
}; };
&reg_3p0 {
vin-supply = <&sw2_reg>;
};
&snvs_poweroff { &snvs_poweroff {
status = "okay"; status = "okay";
}; };
......
...@@ -159,10 +159,6 @@ &reg_vdd1p1 { ...@@ -159,10 +159,6 @@ &reg_vdd1p1 {
vin-supply = <&vgen6_reg>; vin-supply = <&vgen6_reg>;
}; };
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 { &reg_vdd2p5 {
vin-supply = <&vgen6_reg>; vin-supply = <&vgen6_reg>;
}; };
......
...@@ -141,10 +141,6 @@ &reg_vdd1p1 { ...@@ -141,10 +141,6 @@ &reg_vdd1p1 {
vin-supply = <&vgen6_reg>; vin-supply = <&vgen6_reg>;
}; };
&reg_vdd3p0 {
vin-supply = <&sw2_reg>;
};
&reg_vdd2p5 { &reg_vdd2p5 {
vin-supply = <&vgen6_reg>; vin-supply = <&vgen6_reg>;
}; };
......
...@@ -49,3 +49,7 @@ memory@80000000 { ...@@ -49,3 +49,7 @@ memory@80000000 {
reg = <0x80000000 0x10000000>; reg = <0x80000000 0x10000000>;
}; };
}; };
&gpmi {
status = "okay";
};
...@@ -37,10 +37,10 @@ cpus { ...@@ -37,10 +37,10 @@ cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu0: cpu@0 { cpu0: cpu@f00 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0xf00>;
}; };
}; };
......
...@@ -175,7 +175,7 @@ ddr: memory-controller@1080000 { ...@@ -175,7 +175,7 @@ ddr: memory-controller@1080000 {
dcfg: syscon@1e00000 { dcfg: syscon@1e00000 {
compatible = "fsl,ls1028a-dcfg", "syscon"; compatible = "fsl,ls1028a-dcfg", "syscon";
reg = <0x0 0x1e00000 0x0 0x10000>; reg = <0x0 0x1e00000 0x0 0x10000>;
big-endian; little-endian;
}; };
rst: syscon@1e60000 { rst: syscon@1e60000 {
......
...@@ -740,7 +740,7 @@ sdma1: dma-controller@30bd0000 { ...@@ -740,7 +740,7 @@ sdma1: dma-controller@30bd0000 {
reg = <0x30bd0000 0x10000>; reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
<&clk IMX8MM_CLK_SDMA1_ROOT>; <&clk IMX8MM_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
......
...@@ -421,7 +421,7 @@ magnetometer@1e { ...@@ -421,7 +421,7 @@ magnetometer@1e {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_imu>; pinctrl-0 = <&pinctrl_imu>;
interrupt-parent = <&gpio3>; interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
vdd-supply = <&reg_3v3_p>; vdd-supply = <&reg_3v3_p>;
vddio-supply = <&reg_3v3_p>; vddio-supply = <&reg_3v3_p>;
}; };
......
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