Commit 3f780bba authored by Bjorn Andersson's avatar Bjorn Andersson

Merge branch 'drivers-fixes-for-6.11' into HEAD

Merge drivers-fixes-for-6.11 branch into drivers-for-6.12 to avoid the
(trivial) merge conflict occuring related to the qcom_pdm_domains
update.
parents 79cb2cb8 924fc22c
...@@ -353,6 +353,8 @@ Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org> ...@@ -353,6 +353,8 @@ Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org>
Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org> Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org>
Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com> Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com>
Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com> Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@linaro.org>
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@somainline.org>
Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru> Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
Koushik <raghavendra.koushik@neterion.com> Koushik <raghavendra.koushik@neterion.com>
......
...@@ -2745,7 +2745,7 @@ F: include/linux/soc/qcom/ ...@@ -2745,7 +2745,7 @@ F: include/linux/soc/qcom/
ARM/QUALCOMM SUPPORT ARM/QUALCOMM SUPPORT
M: Bjorn Andersson <andersson@kernel.org> M: Bjorn Andersson <andersson@kernel.org>
M: Konrad Dybcio <konrad.dybcio@linaro.org> M: Konrad Dybcio <konradybcio@kernel.org>
L: linux-arm-msm@vger.kernel.org L: linux-arm-msm@vger.kernel.org
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
...@@ -7106,7 +7106,7 @@ F: drivers/gpu/drm/tiny/panel-mipi-dbi.c ...@@ -7106,7 +7106,7 @@ F: drivers/gpu/drm/tiny/panel-mipi-dbi.c
DRM DRIVER for Qualcomm Adreno GPUs DRM DRIVER for Qualcomm Adreno GPUs
M: Rob Clark <robdclark@gmail.com> M: Rob Clark <robdclark@gmail.com>
R: Sean Paul <sean@poorly.run> R: Sean Paul <sean@poorly.run>
R: Konrad Dybcio <konrad.dybcio@linaro.org> R: Konrad Dybcio <konradybcio@kernel.org>
L: linux-arm-msm@vger.kernel.org L: linux-arm-msm@vger.kernel.org
L: dri-devel@lists.freedesktop.org L: dri-devel@lists.freedesktop.org
L: freedreno@lists.freedesktop.org L: freedreno@lists.freedesktop.org
...@@ -18771,7 +18771,7 @@ F: include/uapi/drm/qaic_accel.h ...@@ -18771,7 +18771,7 @@ F: include/uapi/drm/qaic_accel.h
QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
M: Bjorn Andersson <andersson@kernel.org> M: Bjorn Andersson <andersson@kernel.org>
M: Konrad Dybcio <konrad.dybcio@linaro.org> M: Konrad Dybcio <konradybcio@kernel.org>
L: linux-pm@vger.kernel.org L: linux-pm@vger.kernel.org
L: linux-arm-msm@vger.kernel.org L: linux-arm-msm@vger.kernel.org
S: Maintained S: Maintained
......
...@@ -73,7 +73,7 @@ int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending) ...@@ -73,7 +73,7 @@ int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending)
struct arm_smccc_res get_wq_res; struct arm_smccc_res get_wq_res;
struct arm_smccc_args get_wq_ctx = {0}; struct arm_smccc_args get_wq_ctx = {0};
get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, get_wq_ctx.args[0] = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,
ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP, ARM_SMCCC_SMC_64, ARM_SMCCC_OWNER_SIP,
SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_WQ_CTX)); SCM_SMC_FNID(QCOM_SCM_SVC_WAITQ, QCOM_SCM_WAITQ_GET_WQ_CTX));
......
...@@ -40,7 +40,6 @@ struct qcom_tzmem_pool { ...@@ -40,7 +40,6 @@ struct qcom_tzmem_pool {
}; };
struct qcom_tzmem_chunk { struct qcom_tzmem_chunk {
phys_addr_t paddr;
size_t size; size_t size;
struct qcom_tzmem_pool *owner; struct qcom_tzmem_pool *owner;
}; };
...@@ -385,7 +384,6 @@ void *qcom_tzmem_alloc(struct qcom_tzmem_pool *pool, size_t size, gfp_t gfp) ...@@ -385,7 +384,6 @@ void *qcom_tzmem_alloc(struct qcom_tzmem_pool *pool, size_t size, gfp_t gfp)
return NULL; return NULL;
} }
chunk->paddr = gen_pool_virt_to_phys(pool->genpool, vaddr);
chunk->size = size; chunk->size = size;
chunk->owner = pool; chunk->owner = pool;
...@@ -431,25 +429,37 @@ void qcom_tzmem_free(void *vaddr) ...@@ -431,25 +429,37 @@ void qcom_tzmem_free(void *vaddr)
EXPORT_SYMBOL_GPL(qcom_tzmem_free); EXPORT_SYMBOL_GPL(qcom_tzmem_free);
/** /**
* qcom_tzmem_to_phys() - Map the virtual address of a TZ buffer to physical. * qcom_tzmem_to_phys() - Map the virtual address of TZ memory to physical.
* @vaddr: Virtual address of the buffer allocated from a TZ memory pool. * @vaddr: Virtual address of memory allocated from a TZ memory pool.
* *
* Can be used in any context. The address must have been returned by a call * Can be used in any context. The address must point to memory allocated
* to qcom_tzmem_alloc(). * using qcom_tzmem_alloc().
* *
* Returns: Physical address of the buffer. * Returns:
* Physical address mapped from the virtual or 0 if the mapping failed.
*/ */
phys_addr_t qcom_tzmem_to_phys(void *vaddr) phys_addr_t qcom_tzmem_to_phys(void *vaddr)
{ {
struct qcom_tzmem_chunk *chunk; struct qcom_tzmem_chunk *chunk;
struct radix_tree_iter iter;
void __rcu **slot;
phys_addr_t ret;
guard(spinlock_irqsave)(&qcom_tzmem_chunks_lock); guard(spinlock_irqsave)(&qcom_tzmem_chunks_lock);
chunk = radix_tree_lookup(&qcom_tzmem_chunks, (unsigned long)vaddr); radix_tree_for_each_slot(slot, &qcom_tzmem_chunks, &iter, 0) {
if (!chunk) chunk = radix_tree_deref_slot_protected(slot,
return 0; &qcom_tzmem_chunks_lock);
return chunk->paddr; ret = gen_pool_virt_to_phys(chunk->owner->genpool,
(unsigned long)vaddr);
if (ret == -1)
continue;
return ret;
}
return 0;
} }
EXPORT_SYMBOL_GPL(qcom_tzmem_to_phys); EXPORT_SYMBOL_GPL(qcom_tzmem_to_phys);
......
...@@ -77,7 +77,7 @@ config QCOM_PD_MAPPER ...@@ -77,7 +77,7 @@ config QCOM_PD_MAPPER
select QCOM_QMI_HELPERS select QCOM_QMI_HELPERS
select QCOM_PDR_MSG select QCOM_PDR_MSG
select AUXILIARY_BUS select AUXILIARY_BUS
depends on NET && QRTR depends on NET && QRTR && (ARCH_QCOM || COMPILE_TEST)
default QCOM_RPROC_COMMON default QCOM_RPROC_COMMON
help help
The Protection Domain Mapper maps registered services to the domains The Protection Domain Mapper maps registered services to the domains
......
...@@ -349,7 +349,7 @@ static int cmd_db_dev_probe(struct platform_device *pdev) ...@@ -349,7 +349,7 @@ static int cmd_db_dev_probe(struct platform_device *pdev)
return -EINVAL; return -EINVAL;
} }
cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WB); cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WC);
if (!cmd_db_header) { if (!cmd_db_header) {
ret = -ENOMEM; ret = -ENOMEM;
cmd_db_header = NULL; cmd_db_header = NULL;
......
...@@ -517,7 +517,7 @@ static const struct qcom_pdm_domain_data *sm8550_domains[] = { ...@@ -517,7 +517,7 @@ static const struct qcom_pdm_domain_data *sm8550_domains[] = {
NULL, NULL,
}; };
static const struct of_device_id qcom_pdm_domains[] = { static const struct of_device_id qcom_pdm_domains[] __maybe_unused = {
{ .compatible = "qcom,apq8064", .data = NULL, }, { .compatible = "qcom,apq8064", .data = NULL, },
{ .compatible = "qcom,apq8074", .data = NULL, }, { .compatible = "qcom,apq8074", .data = NULL, },
{ .compatible = "qcom,apq8084", .data = NULL, }, { .compatible = "qcom,apq8084", .data = NULL, },
......
...@@ -25,51 +25,6 @@ struct qseecom_client { ...@@ -25,51 +25,6 @@ struct qseecom_client {
u32 app_id; u32 app_id;
}; };
/**
* qseecom_scm_dev() - Get the SCM device associated with the QSEECOM client.
* @client: The QSEECOM client device.
*
* Returns the SCM device under which the provided QSEECOM client device
* operates. This function is intended to be used for DMA allocations.
*/
static inline struct device *qseecom_scm_dev(struct qseecom_client *client)
{
return client->aux_dev.dev.parent->parent;
}
/**
* qseecom_dma_alloc() - Allocate DMA memory for a QSEECOM client.
* @client: The QSEECOM client to allocate the memory for.
* @size: The number of bytes to allocate.
* @dma_handle: Pointer to where the DMA address should be stored.
* @gfp: Allocation flags.
*
* Wrapper function for dma_alloc_coherent(), allocating DMA memory usable for
* TZ/QSEECOM communication. Refer to dma_alloc_coherent() for details.
*/
static inline void *qseecom_dma_alloc(struct qseecom_client *client, size_t size,
dma_addr_t *dma_handle, gfp_t gfp)
{
return dma_alloc_coherent(qseecom_scm_dev(client), size, dma_handle, gfp);
}
/**
* dma_free_coherent() - Free QSEECOM DMA memory.
* @client: The QSEECOM client for which the memory has been allocated.
* @size: The number of bytes allocated.
* @cpu_addr: Virtual memory address to free.
* @dma_handle: DMA memory address to free.
*
* Wrapper function for dma_free_coherent(), freeing memory previously
* allocated with qseecom_dma_alloc(). Refer to dma_free_coherent() for
* details.
*/
static inline void qseecom_dma_free(struct qseecom_client *client, size_t size,
void *cpu_addr, dma_addr_t dma_handle)
{
return dma_free_coherent(qseecom_scm_dev(client), size, cpu_addr, dma_handle);
}
/** /**
* qcom_qseecom_app_send() - Send to and receive data from a given QSEE app. * qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
* @client: The QSEECOM client associated with the target app. * @client: The QSEECOM client associated with the target app.
......
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