Commit 41474e6b authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 49b72ae7 fdb9b087
......@@ -16,6 +16,8 @@
#include <asm/assembler.h>
#include <asm/hardware.h>
#include <asm/arch/pxa-regs.h>
.text
/*
......
......@@ -23,6 +23,7 @@
* 13-Sep-2004 BJD Implemented change of MISCCR
* 14-Sep-2004 BJD Added getpin call
* 14-Sep-2004 BJD Fixed bug in setpin() call
* 30-Sep-2004 BJD Fixed cfgpin() mask bug
*/
......@@ -40,23 +41,20 @@
void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
{
unsigned long base = S3C2410_GPIO_BASE(pin);
unsigned long shift = 1;
unsigned long mask = 3;
unsigned long mask;
unsigned long con;
unsigned long flags;
if (pin < S3C2410_GPIO_BANKB) {
shift = 0;
mask = 1;
mask = 1 << S3C2410_GPIO_OFFSET(pin);
} else {
mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
}
mask <<= S3C2410_GPIO_OFFSET(pin);
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= mask << shift;
con = __raw_readl(base + 0x00);
con &= ~mask;
con |= function;
__raw_writel(con, base + 0x00);
......
......@@ -23,7 +23,6 @@ ENTRY(v5tj_early_abort)
mrc p15, 0, r0, c6, c0, 0 @ get FAR
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #PSR_J_BIT @ Java?
orrne r1, r1, #1 << 11 @ always assume write
movne pc, lr
tst r3, #PSR_T_BIT @ Thumb?
ldrneh r3, [r2] @ read aborted thumb instruction
......
......@@ -27,6 +27,10 @@
#include <linux/watchdog.h>
#include <linux/init.h>
#ifdef CONFIG_ARCH_PXA
#include <asm/arch/pxa-regs.h>
#endif
#include <asm/hardware.h>
#include <asm/bitops.h>
#include <asm/uaccess.h>
......
......@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
#include <asm/arch/pxa-regs.h>
#define BAUD_BASE 921600
......
......@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*
* Changelog:
* 14-Sep-2004 BJD Fixed IRQ_USBOC definition
* 06-Jan-2003 BJD Linux 2.6.0 version
*/
......@@ -18,7 +19,7 @@
/* irq numbers to onboard peripherals */
#define IRQ_USBOC IRQ_EINT19
#define IRQ_USBOC IRQ_EINT18
#define IRQ_IDE0 IRQ_EINT16
#define IRQ_IDE1 IRQ_EINT17
#define IRQ_PCSERIAL1 IRQ_EINT15
......
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