Commit 418abce2 authored by yipechai's avatar yipechai Committed by Alex Deucher

drm/amdgpu: Remove redundant .ras_late_init initialization in some ras blocks

1. Define amdgpu_ras_block_late_init_default in amdgpu_ras.c as
   .ras_late_init common function, which is called when
   .ras_late_init of ras block isn't initialized.
2. Remove the code of using amdgpu_ras_block_late_init to
   initialize .ras_late_init in ras blocks.
Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 867e24ca
...@@ -2457,6 +2457,12 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev, ...@@ -2457,6 +2457,12 @@ int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
return r; return r;
} }
int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
struct ras_common_if *ras_block)
{
return amdgpu_ras_block_late_init(adev, ras_block);
}
/* helper function to remove ras fs node and interrupt handler */ /* helper function to remove ras fs node and interrupt handler */
void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
struct ras_common_if *ras_block) struct ras_common_if *ras_block)
...@@ -2533,6 +2539,7 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) ...@@ -2533,6 +2539,7 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
continue; continue;
} }
obj = node->ras_obj; obj = node->ras_obj;
if (obj->ras_late_init) { if (obj->ras_late_init) {
r = obj->ras_late_init(adev, &obj->ras_comm); r = obj->ras_late_init(adev, &obj->ras_comm);
...@@ -2541,7 +2548,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) ...@@ -2541,7 +2548,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev)
obj->ras_comm.name, r); obj->ras_comm.name, r);
return r; return r;
} }
} } else
amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
} }
return 0; return 0;
......
...@@ -1291,10 +1291,6 @@ static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) ...@@ -1291,10 +1291,6 @@ static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm; adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm;
/* If don't define special ras_late_init function, use default ras_late_init */
if (!adev->mmhub.ras->ras_block.ras_late_init)
adev->mmhub.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
/* If don't define special ras_fini function, use default ras_fini */ /* If don't define special ras_fini function, use default ras_fini */
if (!adev->mmhub.ras->ras_block.ras_fini) if (!adev->mmhub.ras->ras_block.ras_fini)
adev->mmhub.ras->ras_block.ras_fini = amdgpu_mmhub_ras_fini; adev->mmhub.ras->ras_block.ras_fini = amdgpu_mmhub_ras_fini;
......
...@@ -163,7 +163,6 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = { ...@@ -163,7 +163,6 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = {
.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
}, },
.hw_ops = &hdp_v4_0_ras_hw_ops, .hw_ops = &hdp_v4_0_ras_hw_ops,
.ras_late_init = amdgpu_ras_block_late_init,
.ras_fini = amdgpu_hdp_ras_fini, .ras_fini = amdgpu_hdp_ras_fini,
}, },
}; };
......
...@@ -71,7 +71,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = { ...@@ -71,7 +71,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
}, },
.hw_ops = &mca_v3_0_mp0_hw_ops, .hw_ops = &mca_v3_0_mp0_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_late_init = amdgpu_ras_block_late_init,
.ras_fini = mca_v3_0_mp0_ras_fini, .ras_fini = mca_v3_0_mp0_ras_fini,
}, },
}; };
...@@ -104,7 +103,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = { ...@@ -104,7 +103,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
}, },
.hw_ops = &mca_v3_0_mp1_hw_ops, .hw_ops = &mca_v3_0_mp1_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_late_init = amdgpu_ras_block_late_init,
.ras_fini = mca_v3_0_mp1_ras_fini, .ras_fini = mca_v3_0_mp1_ras_fini,
}, },
}; };
...@@ -137,7 +135,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = { ...@@ -137,7 +135,6 @@ struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
}, },
.hw_ops = &mca_v3_0_mpio_hw_ops, .hw_ops = &mca_v3_0_mpio_hw_ops,
.ras_block_match = mca_v3_0_ras_block_match, .ras_block_match = mca_v3_0_ras_block_match,
.ras_late_init = amdgpu_ras_block_late_init,
.ras_fini = mca_v3_0_mpio_ras_fini, .ras_fini = mca_v3_0_mpio_ras_fini,
}, },
}; };
......
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