Commit 4328a218 authored by Jonathan Liu's avatar Jonathan Liu Committed by Maxime Ripard

clk: sunxi-ng: sun4i: Export video PLLs

The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.
Signed-off-by: default avatarJonathan Liu <net147@gmail.com>
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 553c7d5b
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
#define CLK_PLL_AUDIO_4X 6 #define CLK_PLL_AUDIO_4X 6
#define CLK_PLL_AUDIO_8X 7 #define CLK_PLL_AUDIO_8X 7
#define CLK_PLL_VIDEO0 8 #define CLK_PLL_VIDEO0 8
#define CLK_PLL_VIDEO0_2X 9 /* The PLL_VIDEO0_2X clock is exported */
#define CLK_PLL_VE 10 #define CLK_PLL_VE 10
#define CLK_PLL_DDR_BASE 11 #define CLK_PLL_DDR_BASE 11
#define CLK_PLL_DDR 12 #define CLK_PLL_DDR 12
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
#define CLK_PLL_PERIPH 15 #define CLK_PLL_PERIPH 15
#define CLK_PLL_PERIPH_SATA 16 #define CLK_PLL_PERIPH_SATA 16
#define CLK_PLL_VIDEO1 17 #define CLK_PLL_VIDEO1 17
#define CLK_PLL_VIDEO1_2X 18 /* The PLL_VIDEO1_2X clock is exported */
#define CLK_PLL_GPU 19 #define CLK_PLL_GPU 19
/* The CPU clock is exported */ /* The CPU clock is exported */
......
...@@ -43,6 +43,8 @@ ...@@ -43,6 +43,8 @@
#define _DT_BINDINGS_CLK_SUN4I_A10_H_ #define _DT_BINDINGS_CLK_SUN4I_A10_H_
#define CLK_HOSC 1 #define CLK_HOSC 1
#define CLK_PLL_VIDEO0_2X 9
#define CLK_PLL_VIDEO1_2X 18
#define CLK_CPU 20 #define CLK_CPU 20
/* AHB Gates */ /* AHB Gates */
......
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