Commit 437db590 authored by Kevin Wells's avatar Kevin Wells

ARM: LPC32XX: Initial arch header files

Header files for the LPC32xx arch
Signed-off-by: default avatarKevin Wells <wellsk40@gmail.com>
Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
parent d15aa2cc
/*
* arch/arm/mach-lpc32xx/include/mach/clkdev.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_CLKDEV_H
#define __ASM_ARCH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/gpio.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#include <asm-generic/gpio.h>
/*
* Note!
* Muxed GP pins need to be setup to the GP state in the board level
* code prior to using this driver.
* GPI pins : 28xP3 group
* GPO pins : 24xP3 group
* GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
*/
#define LPC32XX_GPIO_P0_MAX 8
#define LPC32XX_GPIO_P1_MAX 24
#define LPC32XX_GPIO_P2_MAX 13
#define LPC32XX_GPIO_P3_MAX 6
#define LPC32XX_GPI_P3_MAX 28
#define LPC32XX_GPO_P3_MAX 24
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
/*
* A specific GPIO can be selected with this macro
* ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
* See the LPC32x0 User's guide for GPIO group numbers
*/
#define LPC32XX_GPIO(x, y) ((x) + (y))
static inline int gpio_get_value(unsigned gpio)
{
return __gpio_get_value(gpio);
}
static inline void gpio_set_value(unsigned gpio, int value)
{
__gpio_set_value(gpio, value);
}
static inline int gpio_cansleep(unsigned gpio)
{
return __gpio_cansleep(gpio);
}
static inline int gpio_to_irq(unsigned gpio)
{
return __gpio_to_irq(gpio);
}
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/hardware.h
*
* Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Start of virtual addresses for IO devices
*/
#define IO_BASE 0xF0000000
/*
* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
*/
#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
IO_BASE)
#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
#endif
/*
* PNX4008-specific tweaks for I2C IP3204 block
*
* Author: Vitaly Wool <vwool@ru.mvista.com>
*
* 2005 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_I2C_H
#define __ASM_ARCH_I2C_H
enum {
mstatus_tdi = 0x00000001,
mstatus_afi = 0x00000002,
mstatus_nai = 0x00000004,
mstatus_drmi = 0x00000008,
mstatus_active = 0x00000020,
mstatus_scl = 0x00000040,
mstatus_sda = 0x00000080,
mstatus_rff = 0x00000100,
mstatus_rfe = 0x00000200,
mstatus_tff = 0x00000400,
mstatus_tfe = 0x00000800,
};
enum {
mcntrl_tdie = 0x00000001,
mcntrl_afie = 0x00000002,
mcntrl_naie = 0x00000004,
mcntrl_drmie = 0x00000008,
mcntrl_daie = 0x00000020,
mcntrl_rffie = 0x00000040,
mcntrl_tffie = 0x00000080,
mcntrl_reset = 0x00000100,
mcntrl_cdbmode = 0x00000400,
};
enum {
rw_bit = 1 << 0,
start_bit = 1 << 8,
stop_bit = 1 << 9,
};
#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
#define I2C_CHIP_NAME "PNX4008-I2C"
#endif /* __ASM_ARCH_I2C_H */
/*
* arch/arm/mach-lpc32xx/include/mach/io.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/irqs.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_IRQS_H
#define __ASM_ARM_ARCH_IRQS_H
#define LPC32XX_SIC1_IRQ(n) (32 + (n))
#define LPC32XX_SIC2_IRQ(n) (64 + (n))
/*
* MIC interrupts
*/
#define IRQ_LPC32XX_SUB1IRQ 0
#define IRQ_LPC32XX_SUB2IRQ 1
#define IRQ_LPC32XX_PWM3 3
#define IRQ_LPC32XX_PWM4 4
#define IRQ_LPC32XX_HSTIMER 5
#define IRQ_LPC32XX_WATCH 6
#define IRQ_LPC32XX_UART_IIR3 7
#define IRQ_LPC32XX_UART_IIR4 8
#define IRQ_LPC32XX_UART_IIR5 9
#define IRQ_LPC32XX_UART_IIR6 10
#define IRQ_LPC32XX_FLASH 11
#define IRQ_LPC32XX_SD1 13
#define IRQ_LPC32XX_LCD 14
#define IRQ_LPC32XX_SD0 15
#define IRQ_LPC32XX_TIMER0 16
#define IRQ_LPC32XX_TIMER1 17
#define IRQ_LPC32XX_TIMER2 18
#define IRQ_LPC32XX_TIMER3 19
#define IRQ_LPC32XX_SSP0 20
#define IRQ_LPC32XX_SSP1 21
#define IRQ_LPC32XX_I2S0 22
#define IRQ_LPC32XX_I2S1 23
#define IRQ_LPC32XX_UART_IIR7 24
#define IRQ_LPC32XX_UART_IIR2 25
#define IRQ_LPC32XX_UART_IIR1 26
#define IRQ_LPC32XX_MSTIMER 27
#define IRQ_LPC32XX_DMA 28
#define IRQ_LPC32XX_ETHERNET 29
#define IRQ_LPC32XX_SUB1FIQ 30
#define IRQ_LPC32XX_SUB2FIQ 31
/*
* SIC1 interrupts start at offset 32
*/
#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
#define IRQ_LPC32XX_SPI2 LPC32XX_SIC1_IRQ(12)
#define IRQ_LPC32XX_PLLUSB LPC32XX_SIC1_IRQ(13)
#define IRQ_LPC32XX_PLLHCLK LPC32XX_SIC1_IRQ(14)
#define IRQ_LPC32XX_PLL397 LPC32XX_SIC1_IRQ(17)
#define IRQ_LPC32XX_I2C_2 LPC32XX_SIC1_IRQ(18)
#define IRQ_LPC32XX_I2C_1 LPC32XX_SIC1_IRQ(19)
#define IRQ_LPC32XX_RTC LPC32XX_SIC1_IRQ(20)
#define IRQ_LPC32XX_KEY LPC32XX_SIC1_IRQ(22)
#define IRQ_LPC32XX_SPI1 LPC32XX_SIC1_IRQ(23)
#define IRQ_LPC32XX_SW LPC32XX_SIC1_IRQ(24)
#define IRQ_LPC32XX_USB_OTG_TIMER LPC32XX_SIC1_IRQ(25)
#define IRQ_LPC32XX_USB_OTG_ATX LPC32XX_SIC1_IRQ(26)
#define IRQ_LPC32XX_USB_HOST LPC32XX_SIC1_IRQ(27)
#define IRQ_LPC32XX_USB_DEV_DMA LPC32XX_SIC1_IRQ(28)
#define IRQ_LPC32XX_USB_DEV_LP LPC32XX_SIC1_IRQ(29)
#define IRQ_LPC32XX_USB_DEV_HP LPC32XX_SIC1_IRQ(30)
#define IRQ_LPC32XX_USB_I2C LPC32XX_SIC1_IRQ(31)
/*
* SIC2 interrupts start at offset 64
*/
#define IRQ_LPC32XX_GPIO_00 LPC32XX_SIC2_IRQ(0)
#define IRQ_LPC32XX_GPIO_01 LPC32XX_SIC2_IRQ(1)
#define IRQ_LPC32XX_GPIO_02 LPC32XX_SIC2_IRQ(2)
#define IRQ_LPC32XX_GPIO_03 LPC32XX_SIC2_IRQ(3)
#define IRQ_LPC32XX_GPIO_04 LPC32XX_SIC2_IRQ(4)
#define IRQ_LPC32XX_GPIO_05 LPC32XX_SIC2_IRQ(5)
#define IRQ_LPC32XX_SPI2_DATAIN LPC32XX_SIC2_IRQ(6)
#define IRQ_LPC32XX_U2_HCTS LPC32XX_SIC2_IRQ(7)
#define IRQ_LPC32XX_P0_P1_IRQ LPC32XX_SIC2_IRQ(8)
#define IRQ_LPC32XX_GPI_08 LPC32XX_SIC2_IRQ(9)
#define IRQ_LPC32XX_GPI_09 LPC32XX_SIC2_IRQ(10)
#define IRQ_LPC32XX_GPI_19 LPC32XX_SIC2_IRQ(11)
#define IRQ_LPC32XX_U7_HCTS LPC32XX_SIC2_IRQ(12)
#define IRQ_LPC32XX_GPI_07 LPC32XX_SIC2_IRQ(15)
#define IRQ_LPC32XX_SDIO LPC32XX_SIC2_IRQ(18)
#define IRQ_LPC32XX_U5_RX LPC32XX_SIC2_IRQ(19)
#define IRQ_LPC32XX_SPI1_DATAIN LPC32XX_SIC2_IRQ(20)
#define IRQ_LPC32XX_GPI_00 LPC32XX_SIC2_IRQ(22)
#define IRQ_LPC32XX_GPI_01 LPC32XX_SIC2_IRQ(23)
#define IRQ_LPC32XX_GPI_02 LPC32XX_SIC2_IRQ(24)
#define IRQ_LPC32XX_GPI_03 LPC32XX_SIC2_IRQ(25)
#define IRQ_LPC32XX_GPI_04 LPC32XX_SIC2_IRQ(26)
#define IRQ_LPC32XX_GPI_05 LPC32XX_SIC2_IRQ(27)
#define IRQ_LPC32XX_GPI_06 LPC32XX_SIC2_IRQ(28)
#define IRQ_LPC32XX_SYSCLK LPC32XX_SIC2_IRQ(31)
#define NR_IRQS 96
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/memory.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset of bank 0
*/
#define PHYS_OFFSET UL(0x80000000)
#endif
This diff is collapsed.
/*
* arch/arm/mach-lpc32xx/include/mach/system.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
static void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
extern void lpc32xx_watchdog_reset(void);
switch (mode) {
case 's':
case 'h':
printk(KERN_CRIT "RESET: Rebooting system\n");
/* Disable interrupts */
local_irq_disable();
lpc32xx_watchdog_reset();
break;
default:
/* Do nothing */
break;
}
/* Wait for watchdog to reset system */
while (1)
;
}
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/timex.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
/*
* Rate in Hz of the main system oscillator. This value should match
* the value 'MAIN_OSC_FREQ' in platform.h
*/
#define CLOCK_TICK_RATE 13000000
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/uncompress.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
#define __ASM_ARM_ARCH_UNCOMPRESS_H
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
/*
* Uncompress output is hardcoded to standard UART 5
*/
#define UART_FIFO_CTL_TX_RESET (1 << 2)
#define UART_STATUS_TX_MT (1 << 6)
#define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
#define LPC32XX_UART_DLLFIFO_O 0x00
#define LPC32XX_UART_IIRFCR_O 0x08
#define LPC32XX_UART_LSR_O 0x14
static inline void putc(int ch)
{
/* Wait for transmit FIFO to empty */
while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
UART_STATUS_TX_MT) == 0)
;
__raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
}
static inline void flush(void)
{
__raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
}
/* NULL functions; we don't presently need them */
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif
/*
* arch/arm/mach-lpc32xx/include/mach/vmalloc.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END 0xF0000000
#endif
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