Commit 43b812d9 authored by Paul Mackerras's avatar Paul Mackerras

Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-next

This merges in the ppc-kvm topic branch of the powerpc repository
to get some changes on which future patches will depend, in particular
some new exports and TEXASR bit definitions.
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
parents 7b0e827c eacbb218
...@@ -141,4 +141,7 @@ unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip); ...@@ -141,4 +141,7 @@ unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip);
void pnv_power9_force_smt4_catch(void); void pnv_power9_force_smt4_catch(void);
void pnv_power9_force_smt4_release(void); void pnv_power9_force_smt4_release(void);
void tm_enable(void);
void tm_disable(void);
void tm_abort(uint8_t cause);
#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */ #endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
...@@ -146,6 +146,12 @@ ...@@ -146,6 +146,12 @@
#define MSR_64BIT 0 #define MSR_64BIT 0
#endif #endif
/* Condition Register related */
#define CR0_SHIFT 28
#define CR0_MASK 0xF
#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */
/* Power Management - Processor Stop Status and Control Register Fields */ /* Power Management - Processor Stop Status and Control Register Fields */
#define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */
#define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
...@@ -239,13 +245,27 @@ ...@@ -239,13 +245,27 @@
#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */
#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */
#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */
#define TEXASR_ABORT __MASK(63-31) /* terminated by tabort or treclaim */
#define TEXASR_SUSP __MASK(63-32) /* tx failed in suspended state */ #define TEXASR_FC_LG (63 - 7) /* Failure Code */
#define TEXASR_HV __MASK(63-34) /* MSR[HV] when failure occurred */ #define TEXASR_AB_LG (63 - 31) /* Abort */
#define TEXASR_PR __MASK(63-35) /* MSR[PR] when failure occurred */ #define TEXASR_SU_LG (63 - 32) /* Suspend */
#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ #define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/
#define TEXASR_EXACT __MASK(63-37) /* TFIAR value is exact */ #define TEXASR_PR_LG (63 - 35) /* Privilege level */
#define TEXASR_FS_LG (63 - 36) /* failure summary */
#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */
#define TEXASR_ROT_LG (63 - 38) /* ROT bit */
#define TEXASR_ABORT __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
#define TEXASR_SUSP __MASK(TEXASR_SU_LG) /* tx failed in suspended state */
#define TEXASR_HV __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
#define TEXASR_PR __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
#define TEXASR_FS __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
#define TEXASR_EXACT __MASK(TEXASR_EX_LG) /* TFIAR value is exact */
#define TEXASR_ROT __MASK(TEXASR_ROT_LG)
#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG)
#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */
#define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_TIDR 144 /* Thread ID register */
#define SPRN_CTRLF 0x088 #define SPRN_CTRLF 0x088
#define SPRN_CTRLT 0x098 #define SPRN_CTRLT 0x098
......
...@@ -10,12 +10,10 @@ ...@@ -10,12 +10,10 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
extern void tm_enable(void);
extern void tm_reclaim(struct thread_struct *thread, extern void tm_reclaim(struct thread_struct *thread,
uint8_t cause); uint8_t cause);
extern void tm_reclaim_current(uint8_t cause); extern void tm_reclaim_current(uint8_t cause);
extern void tm_recheckpoint(struct thread_struct *thread); extern void tm_recheckpoint(struct thread_struct *thread);
extern void tm_abort(uint8_t cause);
extern void tm_save_sprs(struct thread_struct *thread); extern void tm_save_sprs(struct thread_struct *thread);
extern void tm_restore_sprs(struct thread_struct *thread); extern void tm_restore_sprs(struct thread_struct *thread);
......
...@@ -154,6 +154,7 @@ unsigned long msr_check_and_set(unsigned long bits) ...@@ -154,6 +154,7 @@ unsigned long msr_check_and_set(unsigned long bits)
return newmsr; return newmsr;
} }
EXPORT_SYMBOL_GPL(msr_check_and_set);
void __msr_check_and_clear(unsigned long bits) void __msr_check_and_clear(unsigned long bits)
{ {
......
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/reg.h> #include <asm/reg.h>
#include <asm/bug.h> #include <asm/bug.h>
#include <asm/export.h>
#ifdef CONFIG_VSX #ifdef CONFIG_VSX
/* See fpu.S, this is borrowed from there */ /* See fpu.S, this is borrowed from there */
...@@ -55,6 +56,16 @@ _GLOBAL(tm_enable) ...@@ -55,6 +56,16 @@ _GLOBAL(tm_enable)
or r4, r4, r3 or r4, r4, r3
mtmsrd r4 mtmsrd r4
1: blr 1: blr
EXPORT_SYMBOL_GPL(tm_enable);
_GLOBAL(tm_disable)
mfmsr r4
li r3, MSR_TM >> 32
sldi r3, r3, 32
andc r4, r4, r3
mtmsrd r4
blr
EXPORT_SYMBOL_GPL(tm_disable);
_GLOBAL(tm_save_sprs) _GLOBAL(tm_save_sprs)
mfspr r0, SPRN_TFHAR mfspr r0, SPRN_TFHAR
...@@ -78,6 +89,7 @@ _GLOBAL(tm_restore_sprs) ...@@ -78,6 +89,7 @@ _GLOBAL(tm_restore_sprs)
_GLOBAL(tm_abort) _GLOBAL(tm_abort)
TABORT(R3) TABORT(R3)
blr blr
EXPORT_SYMBOL_GPL(tm_abort);
/* void tm_reclaim(struct thread_struct *thread, /* void tm_reclaim(struct thread_struct *thread,
* uint8_t cause) * uint8_t cause)
......
...@@ -64,6 +64,7 @@ ...@@ -64,6 +64,7 @@
#include <asm/trace.h> #include <asm/trace.h>
#include <asm/ps3.h> #include <asm/ps3.h>
#include <asm/pte-walk.h> #include <asm/pte-walk.h>
#include <asm/asm-prototypes.h>
#ifdef DEBUG #ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt) #define DBG(fmt...) udbg_printf(fmt)
......
...@@ -7,9 +7,8 @@ ...@@ -7,9 +7,8 @@
* 2 of the License, or (at your option) any later version. * 2 of the License, or (at your option) any later version.
*/ */
#include <asm/ppc-opcode.h> #include <asm/ppc-opcode.h>
#include <asm/reg.h>
#define CR0_SHIFT 28
#define CR0_MASK 0xF
/* /*
* Copy/paste instructions: * Copy/paste instructions:
* *
......
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