Commit 43f53b19 authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Kishon Vijay Abraham I

phy: phy-mt65xx-usb3: fix test fail of HS receiver sensitivity

when use the default value 8 of RG_USB20_SQTH, the HS receiver
sensitivity test of HQA will fail, set it as 2 to fix up the
issue.
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 3e46c397
...@@ -49,6 +49,8 @@ ...@@ -49,6 +49,8 @@
#define PA6_RG_U2_ISO_EN BIT(31) #define PA6_RG_U2_ISO_EN BIT(31)
#define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
#define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020) #define U3P_U2PHYACR4 (SSUSB_SIFSLV_U2PHY_COM_BASE + 0x0020)
#define P2C_RG_USB20_GPIO_CTL BIT(9) #define P2C_RG_USB20_GPIO_CTL BIT(9)
...@@ -165,9 +167,10 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy, ...@@ -165,9 +167,10 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
writel(tmp, port_base + U3P_U2PHYDTM0); writel(tmp, port_base + U3P_U2PHYDTM0);
} }
/* DP/DM BC1.1 path Disable */
tmp = readl(port_base + U3P_USBPHYACR6); tmp = readl(port_base + U3P_USBPHYACR6);
tmp &= ~PA6_RG_U2_BC11_SW_EN; tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
tmp &= ~PA6_RG_U2_SQTH;
tmp |= PA6_RG_U2_SQTH_VAL(2);
writel(tmp, port_base + U3P_USBPHYACR6); writel(tmp, port_base + U3P_USBPHYACR6);
tmp = readl(port_base + U3P_U3PHYA_DA_REG0); tmp = readl(port_base + U3P_U3PHYA_DA_REG0);
......
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