Commit 443c7f3c authored by Jinzhou.Su's avatar Jinzhou.Su Committed by Alex Deucher

drm/amdgpu: add read amdgpu_gfxoff status in debugfs

 Add interface for SMU12 device, used by UMR.

v2: fix code style
Signed-off-by: default avatarJinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ece96a1
...@@ -1073,6 +1073,57 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu ...@@ -1073,6 +1073,57 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu
} }
/**
* amdgpu_debugfs_regs_gfxoff_status - read gfxoff status
*
* @f: open file handle
* @buf: User buffer to store read data in
* @size: Number of bytes to read
* @pos: Offset to seek to
*/
static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = file_inode(f)->i_private;
ssize_t result = 0;
int r;
if (size & 0x3 || *pos & 0x3)
return -EINVAL;
r = pm_runtime_get_sync(adev->ddev->dev);
if (r < 0)
return r;
while (size) {
uint32_t value;
r = amdgpu_get_gfx_off_status(adev, &value);
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
return r;
}
r = put_user(value, (uint32_t *)buf);
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
return r;
}
result += 4;
buf += 4;
*pos += 4;
size -= 4;
}
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
return result;
}
static const struct file_operations amdgpu_debugfs_regs_fops = { static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_read, .read = amdgpu_debugfs_regs_read,
...@@ -1123,7 +1174,9 @@ static const struct file_operations amdgpu_debugfs_gpr_fops = { ...@@ -1123,7 +1174,9 @@ static const struct file_operations amdgpu_debugfs_gpr_fops = {
static const struct file_operations amdgpu_debugfs_gfxoff_fops = { static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.read = amdgpu_debugfs_gfxoff_read,
.write = amdgpu_debugfs_gfxoff_write, .write = amdgpu_debugfs_gfxoff_write,
.llseek = default_llseek
}; };
static const struct file_operations *debugfs_regs[] = { static const struct file_operations *debugfs_regs[] = {
......
...@@ -578,6 +578,20 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) ...@@ -578,6 +578,20 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
mutex_unlock(&adev->gfx.gfx_off_mutex); mutex_unlock(&adev->gfx.gfx_off_mutex);
} }
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
{
int r = 0;
mutex_lock(&adev->gfx.gfx_off_mutex);
r = smu_get_status_gfxoff(adev, value);
mutex_unlock(&adev->gfx.gfx_off_mutex);
return r;
}
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev) int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
{ {
int r; int r;
......
...@@ -378,6 +378,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, ...@@ -378,6 +378,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
int pipe, int queue); int pipe, int queue);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev); int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
void amdgpu_gfx_ras_fini(struct amdgpu_device *adev); void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
......
...@@ -239,6 +239,19 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t ...@@ -239,6 +239,19 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t
return ret; return ret;
} }
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
{
int ret = 0;
struct smu_context *smu = &adev->smu;
if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
*value = smu_get_gfx_off_status(smu);
else
ret = -EINVAL;
return ret;
}
int smu_set_soft_freq_range(struct smu_context *smu, int smu_set_soft_freq_range(struct smu_context *smu,
enum smu_clk_type clk_type, enum smu_clk_type clk_type,
uint32_t min, uint32_t min,
......
...@@ -555,6 +555,7 @@ struct pptable_funcs { ...@@ -555,6 +555,7 @@ struct pptable_funcs {
int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
int (*gfx_off_control)(struct smu_context *smu, bool enable); int (*gfx_off_control)(struct smu_context *smu, bool enable);
uint32_t (*get_gfx_off_status)(struct smu_context *smu);
int (*register_irq_handler)(struct smu_context *smu); int (*register_irq_handler)(struct smu_context *smu);
int (*set_azalia_d3_pme)(struct smu_context *smu); int (*set_azalia_d3_pme)(struct smu_context *smu);
int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
...@@ -755,4 +756,6 @@ int smu_get_uclk_dpm_states(struct smu_context *smu, ...@@ -755,4 +756,6 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
int smu_get_dpm_clock_table(struct smu_context *smu, int smu_get_dpm_clock_table(struct smu_context *smu,
struct dpm_clocks *clock_table); struct dpm_clocks *clock_table);
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
#endif #endif
...@@ -1087,6 +1087,7 @@ static const struct pptable_funcs renoir_ppt_funcs = { ...@@ -1087,6 +1087,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
.send_smc_msg_with_param = smu_v12_0_send_msg_with_param, .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
.gfx_off_control = smu_v12_0_gfx_off_control, .gfx_off_control = smu_v12_0_gfx_off_control,
.get_gfx_off_status = smu_v12_0_get_gfxoff_status,
.init_smc_tables = smu_v12_0_init_smc_tables, .init_smc_tables = smu_v12_0_init_smc_tables,
.fini_smc_tables = smu_v12_0_fini_smc_tables, .fini_smc_tables = smu_v12_0_fini_smc_tables,
.set_default_dpm_table = smu_v12_0_set_default_dpm_tables, .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
......
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
#define smu_set_tool_table_location(smu) smu_ppt_funcs(set_tool_table_location, 0, smu) #define smu_set_tool_table_location(smu) smu_ppt_funcs(set_tool_table_location, 0, smu)
#define smu_notify_memory_pool_location(smu) smu_ppt_funcs(notify_memory_pool_location, 0, smu) #define smu_notify_memory_pool_location(smu) smu_ppt_funcs(notify_memory_pool_location, 0, smu)
#define smu_gfx_off_control(smu, enable) smu_ppt_funcs(gfx_off_control, 0, smu, enable) #define smu_gfx_off_control(smu, enable) smu_ppt_funcs(gfx_off_control, 0, smu, enable)
#define smu_get_gfx_off_status(smu) smu_ppt_funcs(get_gfx_off_status, 0, smu)
#define smu_set_last_dcef_min_deep_sleep_clk(smu) smu_ppt_funcs(set_last_dcef_min_deep_sleep_clk, 0, smu) #define smu_set_last_dcef_min_deep_sleep_clk(smu) smu_ppt_funcs(set_last_dcef_min_deep_sleep_clk, 0, smu)
#define smu_system_features_control(smu, en) smu_ppt_funcs(system_features_control, 0, smu, en) #define smu_system_features_control(smu, en) smu_ppt_funcs(system_features_control, 0, smu, en)
#define smu_init_max_sustainable_clocks(smu) smu_ppt_funcs(init_max_sustainable_clocks, 0, smu) #define smu_init_max_sustainable_clocks(smu) smu_ppt_funcs(init_max_sustainable_clocks, 0, smu)
......
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