Commit 452d9a0f authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'omap-for-v4.6/fixes-not-urgent-signed' of...

Merge tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

Merge "omap non-urgent fixes for v4.6 merge window" from Tony Lindgren:

Fixes for omaps for v4.6 merge window that are not urgent
for the v4.5-rc cycle:

- Add back optimized cpuidle parameters for 34xx that were
  incorrecly removed earlier with cpuidle cleanup

- Fix SSI for omap36xx to get modem working on N950/N9

- A series of omap hwmod fixes via Paul Walmsley <paul@pwsan.com>
  to fix SSI for omap36xx for modem on N950/N9, fix for
  OCP2SCP sysconfig idle mode, and reset data for PCIe on
  dra7

- Fix out of range register access for omap3 control module
  if syscon max_register is initialized like v4.6 will be
  doing

- Fix l4_ls interconnect clocks for 81xx, it should always
  be sysclk6_ck

* tag 'omap-for-v4.6/fixes-not-urgent-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Fix hwmod clock for l4_ls
  ARM: OMAP2+: Fix out of range register access with syscon_config.max_register
  ARM: OMAP3: Add cpuidle parameters table for omap3430
  ARM: DRA7: hwmod: Add reset data for PCIe
  ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
  ARM: OMAP2+: hwmod data: Add SSI data for omap36xx
parents 59e43052 4f5395f0
...@@ -36,7 +36,6 @@ ...@@ -36,7 +36,6 @@
static void __iomem *omap2_ctrl_base; static void __iomem *omap2_ctrl_base;
static s16 omap2_ctrl_offset; static s16 omap2_ctrl_offset;
static struct regmap *omap2_ctrl_syscon;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
struct omap3_scratchpad { struct omap3_scratchpad {
...@@ -166,16 +165,9 @@ u16 omap_ctrl_readw(u16 offset) ...@@ -166,16 +165,9 @@ u16 omap_ctrl_readw(u16 offset)
u32 omap_ctrl_readl(u16 offset) u32 omap_ctrl_readl(u16 offset)
{ {
u32 val;
offset &= 0xfffc; offset &= 0xfffc;
if (!omap2_ctrl_syscon)
val = readl_relaxed(omap2_ctrl_base + offset);
else
regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
&val);
return val; return readl_relaxed(omap2_ctrl_base + offset);
} }
void omap_ctrl_writeb(u8 val, u16 offset) void omap_ctrl_writeb(u8 val, u16 offset)
...@@ -207,11 +199,7 @@ void omap_ctrl_writew(u16 val, u16 offset) ...@@ -207,11 +199,7 @@ void omap_ctrl_writew(u16 val, u16 offset)
void omap_ctrl_writel(u32 val, u16 offset) void omap_ctrl_writel(u32 val, u16 offset)
{ {
offset &= 0xfffc; offset &= 0xfffc;
if (!omap2_ctrl_syscon) writel_relaxed(val, omap2_ctrl_base + offset);
writel_relaxed(val, omap2_ctrl_base + offset);
else
regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
val);
} }
#ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3
...@@ -715,8 +703,6 @@ int __init omap_control_init(void) ...@@ -715,8 +703,6 @@ int __init omap_control_init(void)
if (IS_ERR(syscon)) if (IS_ERR(syscon))
return PTR_ERR(syscon); return PTR_ERR(syscon);
omap2_ctrl_syscon = syscon;
if (of_get_child_by_name(scm_conf, "clocks")) { if (of_get_child_by_name(scm_conf, "clocks")) {
ret = omap2_clk_provider_init(scm_conf, ret = omap2_clk_provider_init(scm_conf,
data->index, data->index,
...@@ -724,9 +710,6 @@ int __init omap_control_init(void) ...@@ -724,9 +710,6 @@ int __init omap_control_init(void)
if (ret) if (ret)
return ret; return ret;
} }
iounmap(omap2_ctrl_base);
omap2_ctrl_base = NULL;
} else { } else {
/* No scm_conf found, direct access */ /* No scm_conf found, direct access */
ret = omap2_clk_provider_init(np, data->index, NULL, ret = omap2_clk_provider_init(np, data->index, NULL,
......
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#include "pm.h" #include "pm.h"
#include "control.h" #include "control.h"
#include "common.h" #include "common.h"
#include "soc.h"
/* Mach specific information to be recorded in the C-state driver_data */ /* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata { struct omap3_idle_statedata {
...@@ -315,6 +316,69 @@ static struct cpuidle_driver omap3_idle_driver = { ...@@ -315,6 +316,69 @@ static struct cpuidle_driver omap3_idle_driver = {
.safe_state_index = 0, .safe_state_index = 0,
}; };
/*
* Numbers based on measurements made in October 2009 for PM optimized kernel
* with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
* and worst case latencies).
*/
static struct cpuidle_driver omap3430_idle_driver = {
.name = "omap3430_idle",
.owner = THIS_MODULE,
.states = {
{
.enter = omap3_enter_idle_bm,
.exit_latency = 110 + 162,
.target_residency = 5,
.name = "C1",
.desc = "MPU ON + CORE ON",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 106 + 180,
.target_residency = 309,
.name = "C2",
.desc = "MPU ON + CORE ON",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 107 + 410,
.target_residency = 46057,
.name = "C3",
.desc = "MPU RET + CORE ON",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 121 + 3374,
.target_residency = 46057,
.name = "C4",
.desc = "MPU OFF + CORE ON",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 855 + 1146,
.target_residency = 46057,
.name = "C5",
.desc = "MPU RET + CORE RET",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 7580 + 4134,
.target_residency = 484329,
.name = "C6",
.desc = "MPU OFF + CORE RET",
},
{
.enter = omap3_enter_idle_bm,
.exit_latency = 7505 + 15274,
.target_residency = 484329,
.name = "C7",
.desc = "MPU OFF + CORE OFF",
},
},
.state_count = ARRAY_SIZE(omap3_idle_data),
.safe_state_index = 0,
};
/* Public functions */ /* Public functions */
/** /**
...@@ -333,5 +397,8 @@ int __init omap3_idle_init(void) ...@@ -333,5 +397,8 @@ int __init omap3_idle_init(void)
if (!mpu_pd || !core_pd || !per_pd || !cam_pd) if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
return -ENODEV; return -ENODEV;
return cpuidle_register(&omap3_idle_driver, NULL); if (cpu_is_omap3430())
return cpuidle_register(&omap3430_idle_driver, NULL);
else
return cpuidle_register(&omap3_idle_driver, NULL);
} }
...@@ -3583,14 +3583,14 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { ...@@ -3583,14 +3583,14 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
.sysc_fields = &omap_hwmod_sysc_type1, .sysc_fields = &omap_hwmod_sysc_type1,
}; };
static struct omap_hwmod_class omap34xx_ssi_hwmod_class = { static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
.name = "ssi", .name = "ssi",
.sysc = &omap34xx_ssi_sysc, .sysc = &omap34xx_ssi_sysc,
}; };
static struct omap_hwmod omap34xx_ssi_hwmod = { static struct omap_hwmod omap3xxx_ssi_hwmod = {
.name = "ssi", .name = "ssi",
.class = &omap34xx_ssi_hwmod_class, .class = &omap3xxx_ssi_hwmod_class,
.clkdm_name = "core_l4_clkdm", .clkdm_name = "core_l4_clkdm",
.main_clk = "ssi_ssr_fck", .main_clk = "ssi_ssr_fck",
.prcm = { .prcm = {
...@@ -3605,9 +3605,9 @@ static struct omap_hwmod omap34xx_ssi_hwmod = { ...@@ -3605,9 +3605,9 @@ static struct omap_hwmod omap34xx_ssi_hwmod = {
}; };
/* L4 CORE -> SSI */ /* L4 CORE -> SSI */
static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = { static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
.master = &omap3xxx_l4_core_hwmod, .master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_ssi_hwmod, .slave = &omap3xxx_ssi_hwmod,
.clk = "ssi_ick", .clk = "ssi_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA, .user = OCP_USER_MPU | OCP_USER_SDMA,
}; };
...@@ -3760,7 +3760,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3760,7 +3760,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_sad2d__l3, &omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp, &omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva, &omap3xxx_l3_main__mmu_iva,
&omap34xx_l4_core__ssi, &omap3xxx_l4_core__ssi,
NULL NULL
}; };
...@@ -3784,6 +3784,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { ...@@ -3784,6 +3784,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_sad2d__l3, &omap3xxx_sad2d__l3,
&omap3xxx_l4_core__mmu_isp, &omap3xxx_l4_core__mmu_isp,
&omap3xxx_l3_main__mmu_iva, &omap3xxx_l3_main__mmu_iva,
&omap3xxx_l4_core__ssi,
NULL NULL
}; };
......
...@@ -1482,8 +1482,7 @@ static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { ...@@ -1482,8 +1482,7 @@ static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
.syss_offs = 0x0014, .syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1, .sysc_fields = &omap_hwmod_sysc_type1,
}; };
...@@ -1532,29 +1531,44 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { ...@@ -1532,29 +1531,44 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
}; };
/* pcie1 */ /* pcie1 */
static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
{ .name = "pcie", .rst_shift = 0 },
};
static struct omap_hwmod dra7xx_pciess1_hwmod = { static struct omap_hwmod dra7xx_pciess1_hwmod = {
.name = "pcie1", .name = "pcie1",
.class = &dra7xx_pciess_hwmod_class, .class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm", .clkdm_name = "pcie_clkdm",
.rst_lines = dra7xx_pciess1_resets,
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
.main_clk = "l4_root_clk_div", .main_clk = "l4_root_clk_div",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
}, },
}; };
/* pcie2 */
static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
{ .name = "pcie", .rst_shift = 1 },
};
/* pcie2 */ /* pcie2 */
static struct omap_hwmod dra7xx_pciess2_hwmod = { static struct omap_hwmod dra7xx_pciess2_hwmod = {
.name = "pcie2", .name = "pcie2",
.class = &dra7xx_pciess_hwmod_class, .class = &dra7xx_pciess_hwmod_class,
.clkdm_name = "pcie_clkdm", .clkdm_name = "pcie_clkdm",
.rst_lines = dra7xx_pciess2_resets,
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
.main_clk = "l4_root_clk_div", .main_clk = "l4_root_clk_div",
.prcm = { .prcm = {
.omap4 = { .omap4 = {
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
.modulemode = MODULEMODE_SWCTRL, .modulemode = MODULEMODE_SWCTRL,
}, },
......
...@@ -429,6 +429,7 @@ static struct omap_hwmod dm81xx_elm_hwmod = { ...@@ -429,6 +429,7 @@ static struct omap_hwmod dm81xx_elm_hwmod = {
static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_elm_hwmod, .slave = &dm81xx_elm_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -478,6 +479,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = { ...@@ -478,6 +479,7 @@ static struct omap_hwmod dm81xx_gpio1_hwmod = {
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_gpio1_hwmod, .slave = &dm81xx_gpio1_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -504,6 +506,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = { ...@@ -504,6 +506,7 @@ static struct omap_hwmod dm81xx_gpio2_hwmod = {
static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_gpio2_hwmod, .slave = &dm81xx_gpio2_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -628,7 +631,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = { ...@@ -628,7 +631,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = {
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer1_hwmod, .slave = &dm814x_timer1_hwmod,
.clk = "timer1_fck", .clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -665,7 +668,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = { ...@@ -665,7 +668,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer2_hwmod, .slave = &dm814x_timer2_hwmod,
.clk = "timer2_fck", .clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1123,6 +1126,7 @@ static struct omap_hwmod dm81xx_mailbox_hwmod = { ...@@ -1123,6 +1126,7 @@ static struct omap_hwmod dm81xx_mailbox_hwmod = {
static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_mailbox_hwmod, .slave = &dm81xx_mailbox_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
...@@ -1157,6 +1161,7 @@ static struct omap_hwmod dm81xx_spinbox_hwmod = { ...@@ -1157,6 +1161,7 @@ static struct omap_hwmod dm81xx_spinbox_hwmod = {
static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
.master = &dm81xx_l4_ls_hwmod, .master = &dm81xx_l4_ls_hwmod,
.slave = &dm81xx_spinbox_hwmod, .slave = &dm81xx_spinbox_hwmod,
.clk = "sysclk6_ck",
.user = OCP_USER_MPU, .user = OCP_USER_MPU,
}; };
......
...@@ -360,6 +360,7 @@ ...@@ -360,6 +360,7 @@
/* PRM.L3INIT_PRM register offsets */ /* PRM.L3INIT_PRM register offsets */
#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010
#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
......
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