Commit 45c94018 authored by Luca Ceresoli's avatar Luca Ceresoli Committed by Stephen Boyd

dt-bindings: clk: versaclock5: convert to yaml

Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Signed-off-by: default avatarLuca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20200723074112.3159-4-luca@lucaceresoli.netReviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent db136ac9
Binding for IDT VersaClock 5,6 programmable i2c clock generators.
The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
generators providing from 3 to 12 output clocks.
==I2C device node==
Required properties:
- compatible: shall be one of
"idt,5p49v5923"
"idt,5p49v5925"
"idt,5p49v5933"
"idt,5p49v5935"
"idt,5p49v6901"
"idt,5p49v6965"
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- 5p49v5923 and
5p49v5925 and
5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
- 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- 5p49v5923 and
5p49v5925 and
5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
For all output ports, a corresponding, optional child node named OUT1,
OUT2, etc. can represent a each output, and the node can be used to
specify the following:
- idt,mode: can be one of the following:
- VC5_LVPECL
- VC5_CMOS
- VC5_HCSL33
- VC5_LVDS
- VC5_CMOS2
- VC5_CMOSD
- VC5_HCSL25
- idt,voltage-microvolts: can be one of the following
- 1800000
- 2500000
- 3300000
- idt,slew-percent: Percent of normal, can be one of
- 80
- 85
- 90
- 100
==Mapping between clock specifier and physical pins==
When referencing the provided clock in the DT using phandle and
clock specifier, the following mapping applies:
5P49V5923:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
5P49V5933:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT4
5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
3 -- OUT3
4 -- OUT4
5P49V6901:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
3 -- OUT3
4 -- OUT4
==Example==
/* 25MHz reference crystal */
ref25: ref25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* IDT 5P49V5923 i2c clock generator */
vc5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
/* Connect XIN input to 25MHz reference */
clocks = <&ref25m>;
clock-names = "xin";
OUT1 {
idt,mode = <VC5_CMOS>;
idt,voltage-microvolts = <1800000>;
idt,slew-percent = <80>;
};
OUT2 {
...
};
...
};
};
/* Consumer referencing the 5P49V5923 pin OUT1 */
consumer {
...
clocks = <&vc5 1>;
...
}
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
description: |
The IDT VersaClock 5 and VersaClock 6 are programmable I2C
clock generators providing from 3 to 12 output clocks.
When referencing the provided clock in the DT using phandle and clock
specifier, the following mapping applies:
- 5P49V5923:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
- 5P49V5933:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT4
- other parts:
0 -- OUT0_SEL_I2CB
1 -- OUT1
2 -- OUT2
3 -- OUT3
4 -- OUT4
maintainers:
- Luca Ceresoli <luca@lucaceresoli.net>
properties:
compatible:
enum:
- idt,5p49v5923
- idt,5p49v5925
- idt,5p49v5933
- idt,5p49v5935
- idt,5p49v6901
- idt,5p49v6965
reg:
description: I2C device address
enum: [ 0x68, 0x6a ]
'#clock-cells':
const: 1
patternProperties:
"^OUT[1-4]$":
type: object
description:
Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
Configuration" in the Versaclock 5/6/6E Family Register Description
and Programming Guide.
properties:
idt,mode:
description:
The output drive mode. Values defined in dt-bindings/clk/versaclock.h
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 6
idt,voltage-microvolt:
description: The output drive voltage.
enum: [ 1800000, 2500000, 3300000 ]
idt,slew-percent:
description: The Slew rate control for CMOS single-ended.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 80, 85, 90, 100 ]
required:
- compatible
- reg
- '#clock-cells'
allOf:
- if:
properties:
compatible:
enum:
- idt,5p49v5933
- idt,5p49v5935
then:
# Devices with builtin crystal + optional external input
properties:
clock-names:
const: clkin
clocks:
maxItems: 1
else:
# Devices without builtin crystal
properties:
clock-names:
minItems: 1
maxItems: 2
items:
enum: [ xin, clkin ]
clocks:
minItems: 1
maxItems: 2
required:
- clock-names
- clocks
examples:
- |
#include <dt-bindings/clk/versaclock.h>
/* 25MHz reference crystal */
ref25: ref25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c@0 {
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
/* IDT 5P49V5923 I2C clock generator */
vc5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
#clock-cells = <1>;
/* Connect XIN input to 25MHz reference */
clocks = <&ref25m>;
clock-names = "xin";
OUT1 {
idt,drive-mode = <VC5_CMOSD>;
idt,voltage-microvolts = <1800000>;
idt,slew-percent = <80>;
};
OUT4 {
idt,drive-mode = <VC5_LVDS>;
};
};
};
/* Consumer referencing the 5P49V5923 pin OUT1 */
consumer {
/* ... */
clocks = <&vc5 1>;
/* ... */
};
...
...@@ -8326,6 +8326,7 @@ F: drivers/input/misc/ideapad_slidebar.c ...@@ -8326,6 +8326,7 @@ F: drivers/input/misc/ideapad_slidebar.c
IDT VersaClock 5 CLOCK DRIVER IDT VersaClock 5 CLOCK DRIVER
M: Luca Ceresoli <luca@lucaceresoli.net> M: Luca Ceresoli <luca@lucaceresoli.net>
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
F: drivers/clk/clk-versaclock5.c F: drivers/clk/clk-versaclock5.c
IEEE 802.15.4 SUBSYSTEM IEEE 802.15.4 SUBSYSTEM
......
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