Commit 45e8c727 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson

arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent

The PCIe controllers on 8180 are cache-coherent. Mark them as such.

Fixes: d20b6c84 ("arm64: dts: qcom: sc8180x: Add PCIe instances")
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231219-topic-8180_pcie_dmac-v1-1-5d00fc1b23fd@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 49b0f4f1
......@@ -1751,6 +1751,7 @@ pcie0: pcie@1c00000 {
phys = <&pcie0_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -1847,6 +1848,7 @@ pcie3: pcie@1c08000 {
phys = <&pcie3_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -1944,6 +1946,7 @@ pcie1: pcie@1c10000 {
phys = <&pcie1_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......@@ -2041,6 +2044,7 @@ pcie2: pcie@1c18000 {
phys = <&pcie2_phy>;
phy-names = "pciephy";
dma-coherent;
status = "disabled";
};
......
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