Merge tag 'xgene-dts-for-v4.5-v1' of https://github.com/AppliedMicro/xgene-next into next/dt64

Merge "DTS changes for X-Gene platforms queued for v4.5" from Duc Dang

This patch set adds DTS entries to support various IPs
for X-Gene v1 and X-Gene v2 SoC:
- X-Gene v1: Enable support for MMC, USB, GPIO controllers,
  I2C controller, L2 Cache topology
- X-Gene v2: Enable support for MMC, USB, GPIO controller,
  I2C controller (with RTC), PCIe controller with GICv2m MSI,
  EDAC, L2 Cache topology, TRNG

* tag 'xgene-dts-for-v4.5-v1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: Add L2 cache topology for APM X-Gene SoC
  arm64: dts: Add RTC DTS entry for X-Gene v2 SoC platform
  arm64: dts: Add Designware I2C controller DTS entries for X-Gene v2 SoC platform
  arm64: dts: Add Designware I2C controller DTS entries for X-Gene v1 SoC
  arm64: dts: Add APM X-Gene v2 SoC EDAC DTS entries
  arm64: dts: Add APM X-Gene v2 SoC Designware GPIO controller DTS entry
  arm64: dts: Add Designware GPIO dts binding for APM X-Gene v1 platform
  arm64: dts: Add APM X-Gene v2 SoC GFC GPIO controller DTS entry
  arm64: dts: Add APM X-Gene v1 SoC GFC GPIO controller DTS entries
  arm64: dts: Add USB nodes for APM X-Gene v2 platforms
  arm64: dts: Add USB nodes for APM X-Gene v1 platforms
  arm64: dts: Add PCIe node for APM X-Gene v2 platforms
  arm64: dts: Add v2m MSI frame nodes for APM X-Gene v2 platforms
  arm64: dts: Add RNG device tree nodes for APM X-Gene v2 platform
  arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block
  arm64: dts: Add the arasan mmc DTS entries for APm X-Gene v2 SoC
  arm64: dts: Add the arasan mmc DTS entries for APM X-Gene v1 SoC

arch/arm64/boot/dts/apm/apm-merlin.dts

@@ -70,3 +70,15 @@ &sgenet0 {
 &xgenet1 {
 	status = "ok";
 };
+
+&mmc0 {
+	status = "ok";
+};
+
+&i2c4 {
+	rtc68: rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+		status = "ok";
+	};
+};

arch/arm64/boot/dts/apm/apm-mustang.dts

@@ -74,3 +74,7 @@ &sgenet1 {
 &xgenet {
 	status = "ok";
 };
+
+&mmc0 {
+	status = "ok";
+};

arch/arm64/boot/dts/apm/apm-storm.dtsi

@@ -25,6 +25,7 @@ cpu@000 {
 			reg = <0x0 0x000>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_0>;
 		};
 		cpu@001 {
 			device_type = "cpu";
@@ -32,6 +33,7 @@ cpu@001 {
 			reg = <0x0 0x001>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_0>;
 		};
 		cpu@100 {
 			device_type = "cpu";
@@ -39,6 +41,7 @@ cpu@100 {
 			reg = <0x0 0x100>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_1>;
 		};
 		cpu@101 {
 			device_type = "cpu";
@@ -46,6 +49,7 @@ cpu@101 {
 			reg = <0x0 0x101>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_1>;
 		};
 		cpu@200 {
 			device_type = "cpu";
@@ -53,6 +57,7 @@ cpu@200 {
 			reg = <0x0 0x200>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_2>;
 		};
 		cpu@201 {
 			device_type = "cpu";
@@ -60,6 +65,7 @@ cpu@201 {
 			reg = <0x0 0x201>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_2>;
 		};
 		cpu@300 {
 			device_type = "cpu";
@@ -67,6 +73,7 @@ cpu@300 {
 			reg = <0x0 0x300>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_3>;
 		};
 		cpu@301 {
 			device_type = "cpu";
@@ -74,6 +81,19 @@ cpu@301 {
 			reg = <0x0 0x301>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x1 0x0000fff8>;
+			next-level-cache = <&xgene_L2_3>;
+		};
+		xgene_L2_0: l2-cache-0 {
+			compatible = "cache";
+		};
+		xgene_L2_1: l2-cache-1 {
+			compatible = "cache";
+		};
+		xgene_L2_2: l2-cache-2 {
+			compatible = "cache";
+		};
+		xgene_L2_3: l2-cache-3 {
+			compatible = "cache";
 		};
 	};
 
@@ -150,6 +170,35 @@ socplldiv2: socplldiv2  {
 				clock-output-names = "socplldiv2";
 			};
 
+			ahbclk: ahbclk@17000000 {
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&socplldiv2 0>;
+				reg = <0x0 0x17000000 0x0 0x2000>;
+				reg-names = "div-reg";
+				divider-offset = <0x164>;
+				divider-width = <0x5>;
+				divider-shift = <0x0>;
+				clock-output-names = "ahbclk";
+			};
+
+			sdioclk: sdioclk@1f2ac000 {
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&socplldiv2 0>;
+				reg = <0x0 0x1f2ac000 0x0 0x1000
+					0x0 0x17000000 0x0 0x2000>;
+				reg-names = "csr-reg", "div-reg";
+				csr-offset = <0x0>;
+				csr-mask = <0x2>;
+				enable-offset = <0x8>;
+				enable-mask = <0x2>;
+				divider-offset = <0x178>;
+				divider-width = <0x8>;
+				divider-shift = <0x0>;
+				clock-output-names = "sdioclk";
+			};
+
 			qmlclk: qmlclk {
 				compatible = "apm,xgene-device-clock";
 				#clock-cells = <1>;
@@ -388,6 +437,20 @@ dmaclk: dmaclk@1f27c000 {
 				reg-names = "csr-reg";
 				clock-output-names = "dmaclk";
 			};
+
+			i2cclk: i2cclk@17000000 {
+				status = "disabled";
+				compatible = "apm,xgene-device-clock";
+				#clock-cells = <1>;
+				clocks = <&ahbclk 0>;
+				reg = <0x0 0x17000000 0x0 0x2000>;
+				reg-names = "csr-reg";
+				csr-offset = <0xc>;
+				csr-mask = <0x4>;
+				enable-offset = <0x10>;
+				enable-mask = <0x4>;
+				clock-output-names = "i2cclk";
+			};
 		};
 
 		msi: msi@79000000 {
@@ -686,6 +749,50 @@ serial3: serial@1c023000 {
 			interrupts = <0x0 0x4f 0x4>;
 		};
 
+		mmc0: mmc@1c000000 {
+			compatible = "arasan,sdhci-4.9a";
+			reg = <0x0 0x1c000000 0x0 0x100>;
+			interrupts = <0x0 0x49 0x4>;
+			dma-coherent;
+			no-1-8-v;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <&sdioclk 0>, <&ahbclk 0>;
+		};
+
+		gfcgpio: gfcgpio0@1701c000 {
+			compatible = "apm,xgene-gpio";
+			reg = <0x0 0x1701c000 0x0 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dwgpio: dwgpio@1c024000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x1c024000 0x0 0x1000>;
+			reg-io-width = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-controller@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+		};
+
+		i2c0: i2c0@10512000 {
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10512000 0x0 0x1000>;
+			interrupts = <0 0x44 0x4>;
+			#clock-cells = <1>;
+			clocks = <&i2cclk 0>;
+			bus_num = <0>;
+		};
+
 		phy1: phy@1f21a000 {
 			compatible = "apm,xgene-phy";
 			reg = <0x0 0x1f21a000 0x0 0x100>;
@@ -760,6 +867,25 @@ sata3: sata@1a800000 {
 			phy-names = "sata-phy";
 		};
 
+		/* Do not change dwusb name, coded for backward compatibility */
+		usb0: dwusb@19000000 {
+			status = "disabled";
+			compatible = "snps,dwc3";
+			reg =  <0x0 0x19000000 0x0 0x100000>;
+			interrupts = <0x0 0x89 0x4>;
+			dma-coherent;
+			dr_mode = "host";
+		};
+
+		usb1: dwusb@19800000 {
+			status = "disabled";
+			compatible = "snps,dwc3";
+			reg =  <0x0 0x19800000 0x0 0x100000>;
+			interrupts = <0x0 0x8a 0x4>;
+			dma-coherent;
+			dr_mode = "host";
+		};
+
 		sbgpio: sbgpio@17001000{
 			compatible = "apm,xgene-gpio-sb";
 			reg = <0x0 0x17001000 0x0 0x400>;