Commit 47d113b3 authored by Stefan Bader's avatar Stefan Bader Committed by Kleber Sacilotto de Souza

UBUNTU: SAUCE: Add missing CPUID_7_EDX defines

BugLink: https://bugs.launchpad.net/bugs/1791080

The 4.4.144 backport of this patch adds the bit definitions
for two AVX-512 features: X86_FEATURE_AVX512_4VNNIW and
X86_FEATURE_AVX512_4FMAPS.
Those bits were not defined before in 4.4, but pick them up
to be in sync with upstream stable.

Fixes: e8e6c1d5 "x86/cpufeatures: Add CPUID_7_EDX CPUID leaf"
Signed-off-by: default avatarStefan Bader <stefan.bader@canonical.com>
Signed-off-by: default avatarKleber Sacilotto de Souza <kleber.souza@canonical.com>
parent 2cff9ebc
...@@ -309,6 +309,9 @@ ...@@ -309,6 +309,9 @@
#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */ #define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
......
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