Commit 48a13191 authored by Jonathan Cameron's avatar Jonathan Cameron

staging: iio: meter: ade7854: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org
parent e48668a3
...@@ -162,7 +162,7 @@ struct ade7854_state { ...@@ -162,7 +162,7 @@ struct ade7854_state {
int bits); int bits);
int irq; int irq;
struct mutex buf_lock; struct mutex buf_lock;
u8 tx[ADE7854_MAX_TX] ____cacheline_aligned; u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN);
u8 rx[ADE7854_MAX_RX]; u8 rx[ADE7854_MAX_RX];
}; };
......
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