Commit 4a33c525 authored by Adam Gruchala's avatar Adam Gruchala Committed by Dan Williams

isci: merge phy substates

Merged states and substates into one state machine, as we always
unconditionally transitioned to the substate machine it was straightforward to
enter that substate from the starting state.
Reported-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarAdam Gruchala <adam.gruchala@intel.com>
[fixed construction, starting_state_enter, and starting check]
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 79e2b6b2
...@@ -932,6 +932,28 @@ static void scic_sds_controller_phy_timer_start(struct scic_sds_controller *scic ...@@ -932,6 +932,28 @@ static void scic_sds_controller_phy_timer_start(struct scic_sds_controller *scic
scic->phy_startup_timer_pending = true; scic->phy_startup_timer_pending = true;
} }
static bool is_phy_starting(struct scic_sds_phy *sci_phy)
{
enum scic_sds_phy_states state;
state = sci_phy->state_machine.current_state_id;
switch (state) {
case SCI_BASE_PHY_STATE_STARTING:
case SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN:
case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF:
case SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL:
return true;
default:
return false;
}
}
/** /**
* scic_sds_controller_start_next_phy - start phy * scic_sds_controller_start_next_phy - start phy
* @scic: controller * @scic: controller
...@@ -975,7 +997,7 @@ static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_contro ...@@ -975,7 +997,7 @@ static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_contro
(sci_phy->is_in_link_training == false && (sci_phy->is_in_link_training == false &&
state == SCI_BASE_PHY_STATE_STOPPED) || state == SCI_BASE_PHY_STATE_STOPPED) ||
(sci_phy->is_in_link_training == true && (sci_phy->is_in_link_training == true &&
state == SCI_BASE_PHY_STATE_STARTING)) { is_phy_starting(sci_phy))) {
is_controller_start_complete = false; is_controller_start_complete = false;
break; break;
} }
......
This diff is collapsed.
...@@ -142,8 +142,6 @@ struct scic_sds_phy { ...@@ -142,8 +142,6 @@ struct scic_sds_phy {
const struct scic_sds_phy_state_handler *state_handlers; const struct scic_sds_phy_state_handler *state_handlers;
struct sci_base_state_machine starting_substate_machine;
/** /**
* This field is the pointer to the transport layer register for the SCU * This field is the pointer to the transport layer register for the SCU
* hardware. * hardware.
...@@ -435,34 +433,6 @@ enum scic_sds_phy_states { ...@@ -435,34 +433,6 @@ enum scic_sds_phy_states {
*/ */
SCI_BASE_PHY_STATE_STARTING, SCI_BASE_PHY_STATE_STARTING,
/**
* This state indicates the the phy is now ready. Thus, the user
* is able to perform IO operations utilizing this phy as long as it
* is currently part of a valid port.
* This state is entered from the STARTING state.
*/
SCI_BASE_PHY_STATE_READY,
/**
* This state indicates that the phy is in the process of being reset.
* In this state no new IO operations are permitted on this phy.
* This state is entered from the READY state.
*/
SCI_BASE_PHY_STATE_RESETTING,
/**
* Simply the final state for the base phy state machine.
*/
SCI_BASE_PHY_STATE_FINAL,
};
/**
* enum scic_sds_phy_starting_substates -
*
*
*/
enum scic_sds_phy_starting_substates {
/** /**
* Initial state * Initial state
*/ */
...@@ -512,8 +482,27 @@ enum scic_sds_phy_starting_substates { ...@@ -512,8 +482,27 @@ enum scic_sds_phy_starting_substates {
* Exit state for this state machine * Exit state for this state machine
*/ */
SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL, SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL,
};
/**
* This state indicates the the phy is now ready. Thus, the user
* is able to perform IO operations utilizing this phy as long as it
* is currently part of a valid port.
* This state is entered from the STARTING state.
*/
SCI_BASE_PHY_STATE_READY,
/**
* This state indicates that the phy is in the process of being reset.
* In this state no new IO operations are permitted on this phy.
* This state is entered from the READY state.
*/
SCI_BASE_PHY_STATE_RESETTING,
/**
* Simply the final state for the base phy state machine.
*/
SCI_BASE_PHY_STATE_FINAL,
};
typedef enum sci_status (*scic_sds_phy_handler_t)(struct scic_sds_phy *); typedef enum sci_status (*scic_sds_phy_handler_t)(struct scic_sds_phy *);
......
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