Commit 4aa4c23f authored by Carlos Santa's avatar Carlos Santa Committed by Rodrigo Vivi

drm/i915: Move HAS_RUNTIME_PM definition to platform

Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions
Signed-off-by: default avatarCarlos Santa <carlos.santa@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 07db6be7
...@@ -655,6 +655,7 @@ struct intel_csr { ...@@ -655,6 +655,7 @@ struct intel_csr {
func(is_preliminary) sep \ func(is_preliminary) sep \
func(has_fbc) sep \ func(has_fbc) sep \
func(has_psr) sep \ func(has_psr) sep \
func(has_runtime_pm) sep \
func(has_pipe_cxsr) sep \ func(has_pipe_cxsr) sep \
func(has_hotplug) sep \ func(has_hotplug) sep \
func(cursor_needs_physical) sep \ func(cursor_needs_physical) sep \
...@@ -2786,10 +2787,7 @@ struct drm_i915_cmd_table { ...@@ -2786,10 +2787,7 @@ struct drm_i915_cmd_table {
#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
IS_KABYLAKE(dev) || IS_BROXTON(dev))
#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
......
...@@ -199,6 +199,7 @@ static const struct intel_device_info intel_ironlake_m_info = { ...@@ -199,6 +199,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
.gen = 6, .num_pipes = 2, \ .gen = 6, .num_pipes = 2, \
.need_gfx_hws = 1, .has_hotplug = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \
.has_fbc = 1, \ .has_fbc = 1, \
.has_runtime_pm = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \ .has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PIPEOFFSETS, \
...@@ -242,6 +243,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { ...@@ -242,6 +243,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
#define VLV_FEATURES \ #define VLV_FEATURES \
.gen = 7, .num_pipes = 2, \ .gen = 7, .num_pipes = 2, \
.has_psr = 1, \ .has_psr = 1, \
.has_runtime_pm = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \ .display_mmio_offset = VLV_DISPLAY_BASE, \
...@@ -258,7 +260,8 @@ static const struct intel_device_info intel_valleyview_info = { ...@@ -258,7 +260,8 @@ static const struct intel_device_info intel_valleyview_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
.has_ddi = 1, \ .has_ddi = 1, \
.has_fpga_dbg = 1, \ .has_fpga_dbg = 1, \
.has_psr = 1 .has_psr = 1, \
.has_runtime_pm = 1
static const struct intel_device_info intel_haswell_info = { static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES, HSW_FEATURES,
...@@ -288,6 +291,7 @@ static const struct intel_device_info intel_cherryview_info = { ...@@ -288,6 +291,7 @@ static const struct intel_device_info intel_cherryview_info = {
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
.is_cherryview = 1, .is_cherryview = 1,
.has_psr = 1, .has_psr = 1,
.has_runtime_pm = 1,
.display_mmio_offset = VLV_DISPLAY_BASE, .display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS, GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS, CURSOR_OFFSETS,
...@@ -316,6 +320,7 @@ static const struct intel_device_info intel_broxton_info = { ...@@ -316,6 +320,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_ddi = 1, .has_ddi = 1,
.has_fpga_dbg = 1, .has_fpga_dbg = 1,
.has_fbc = 1, .has_fbc = 1,
.has_runtime_pm = 1,
.has_pooled_eu = 0, .has_pooled_eu = 0,
GEN_DEFAULT_PIPEOFFSETS, GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS, IVB_CURSOR_OFFSETS,
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment