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Commit 4b60e5f9 authored by Russell King's avatar Russell King
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Merge branches 'consolidate-clksrc', 'consolidate-flash',... 

Merge branches 'consolidate-clksrc', 'consolidate-flash', 'consolidate-generic', 'consolidate-smp', 'consolidate-stmp' and 'consolidate-zones' into consolidate
parents e8765afe 667f390b a35d4e58 4d5336d5 041f10d4 be20902b
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Showing with 412 additions and 10652 deletions
arch/arm/Kconfig
View file @ 4b60e5f9
...@@ -381,16 +381,6 @@ config ARCH_MXS ...@@ -381,16 +381,6 @@ config ARCH_MXS
help help
Support for Freescale MXS-based family of processors Support for Freescale MXS-based family of processors
config ARCH_STMP3XXX
bool "Freescale STMP3xxx"
select CPU_ARM926T
select CLKDEV_LOOKUP
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select USB_ARCH_HAS_EHCI
help
Support for systems based on the Freescale 3xxx CPUs.
config ARCH_NETX config ARCH_NETX
bool "Hilscher NetX based" bool "Hilscher NetX based"
select CLKSRC_MMIO select CLKSRC_MMIO
...@@ -1018,8 +1008,6 @@ source "arch/arm/mach-exynos4/Kconfig" ...@@ -1018,8 +1008,6 @@ source "arch/arm/mach-exynos4/Kconfig"
source "arch/arm/mach-shmobile/Kconfig" source "arch/arm/mach-shmobile/Kconfig"
source "arch/arm/plat-stmp3xxx/Kconfig"
source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig" source "arch/arm/mach-u300/Kconfig"
......
arch/arm/Makefile
View file @ 4b60e5f9
...@@ -185,8 +185,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 ...@@ -185,8 +185,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
machine-$(CONFIG_ARCH_STMP378X) := stmp378x
machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TCC8K) := tcc8k
machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_TEGRA) := tegra
machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U300) := u300
...@@ -207,7 +205,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx ...@@ -207,7 +205,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_S3C64XX) := samsung
plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_ARCH_TCC_926) := tcc
plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_NOMADIK) := nomadik
......
arch/arm/common/sa1111.c
View file @ 4b60e5f9
...@@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = { ...@@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = {
}, },
}; };
void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
{
unsigned int sz = SZ_1M >> PAGE_SHIFT;
size[1] = size[0] - sz;
size[0] = sz;
}
/* /*
* SA1111 interrupt support. Since clearing an IRQ while there are * SA1111 interrupt support. Since clearing an IRQ while there are
* active IRQs causes the interrupt output to pulse, the upper levels * active IRQs causes the interrupt output to pulse, the upper levels
......
arch/arm/configs/mxs_defconfig 0 → 100644
View file @ 4b60e5f9
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_PERF_EVENTS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXS=y
CONFIG_MACH_STMP378X_DEVB=y
CONFIG_MACH_TX28=y
# CONFIG_ARM_THUMB is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
CONFIG_AUTO_ZRELADDR=y
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_CAN=m
CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_DEV=m
CONFIG_CAN_FLEXCAN=m
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ENC28J60=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=m
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_MXS=m
CONFIG_SPI=y
CONFIG_SPI_GPIO=m
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_DISPLAY_SUPPORT=m
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_MXS=y
CONFIG_RTC_CLASS=m
CONFIG_RTC_DRV_DS1307=m
CONFIG_DMADEVICES=y
CONFIG_MXS_DMA=y
CONFIG_EXT3_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
CONFIG_CACHEFILES=m
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_PRINTK_TIME=y
CONFIG_FRAME_WARN=2048
CONFIG_MAGIC_SYSRQ=y
CONFIG_UNUSED_SYMBOLS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_TIMER_STATS=y
CONFIG_PROVE_LOCKING=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_STRICT_DEVMEM=y
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CRC32C=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC7=m
arch/arm/configs/realview-smp_defconfig
View file @ 4b60e5f9
...@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y ...@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ARM_INTEGRATOR=y CONFIG_MTD_PHYSMAP=y
CONFIG_ARM_CHARLCD=y CONFIG_ARM_CHARLCD=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y CONFIG_SMSC_PHY=y
......
arch/arm/configs/realview_defconfig
View file @ 4b60e5f9
...@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y ...@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_ARM_INTEGRATOR=y CONFIG_MTD_PHYSMAP=y
CONFIG_ARM_CHARLCD=y CONFIG_ARM_CHARLCD=y
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y CONFIG_SMSC_PHY=y
......
arch/arm/configs/stmp378x_defconfig deleted 100644 → 0
View file @ e8765afe
CONFIG_EXPERIMENTAL=y
CONFIG_LOCALVERSION="-default"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_STMP3XXX=y
CONFIG_ARCH_STMP378X=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NET_SCHED=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_NAND=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=6144
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=m
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_DEBUG_OBJECTS=y
CONFIG_DEBUG_OBJECTS_SELFTEST=y
CONFIG_DEBUG_OBJECTS_FREE=y
CONFIG_DEBUG_OBJECTS_TIMERS=y
CONFIG_DEBUG_SLAB=y
CONFIG_DEBUG_SLAB_LEAK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_PROVE_LOCKING=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_KOBJECT=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_BOOT_TRACER=y
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
arch/arm/configs/stmp37xx_defconfig deleted 100644 → 0
View file @ e8765afe
CONFIG_EXPERIMENTAL=y
CONFIG_LOCALVERSION="-default"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_STMP3XXX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_MULTIPLE_TABLES=y
CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_MROUTE=y
CONFIG_IP_PIMSM_V1=y
CONFIG_IP_PIMSM_V2=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NET_SCHED=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_STANDALONE is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=6144
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=m
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_BOOT_TRACER=y
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_DEBUG_LL=y
CONFIG_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_AES=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
arch/arm/configs/versatile_defconfig
View file @ 4b60e5f9
...@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y ...@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_ARM_INTEGRATOR=y CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM=y
CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_LEGACY=m
CONFIG_NETDEVICES=y CONFIG_NETDEVICES=y
......
arch/arm/include/asm/dma.h
View file @ 4b60e5f9
...@@ -6,8 +6,10 @@ ...@@ -6,8 +6,10 @@
/* /*
* This is the maximum virtual address which can be DMA'd from. * This is the maximum virtual address which can be DMA'd from.
*/ */
#ifndef MAX_DMA_ADDRESS #ifndef ARM_DMA_ZONE_SIZE
#define MAX_DMA_ADDRESS 0xffffffff #define MAX_DMA_ADDRESS 0xffffffff
#else
#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE)
#endif #endif
#ifdef CONFIG_ISA_DMA_API #ifdef CONFIG_ISA_DMA_API
......
arch/arm/include/asm/memory.h
View file @ 4b60e5f9
...@@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x) ...@@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x)
* allocations. This must be the smallest DMA mask in the system, * allocations. This must be the smallest DMA mask in the system,
* so a successful GFP_DMA allocation will always satisfy this. * so a successful GFP_DMA allocation will always satisfy this.
*/ */
#ifndef ISA_DMA_THRESHOLD #ifndef ARM_DMA_ZONE_SIZE
#define ISA_DMA_THRESHOLD (0xffffffffULL) #define ISA_DMA_THRESHOLD (0xffffffffULL)
#endif #else
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
#ifndef arch_adjust_zones
#define arch_adjust_zones(size,holes) do { } while (0)
#elif !defined(CONFIG_ZONE_DMA)
#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
#endif #endif
/* /*
......
arch/arm/include/asm/sizes.h
View file @ 4b60e5f9
...@@ -16,44 +16,6 @@ ...@@ -16,44 +16,6 @@
/* Size definitions /* Size definitions
* Copyright (C) ARM Limited 1998. All rights reserved. * Copyright (C) ARM Limited 1998. All rights reserved.
*/ */
#include <asm-generic/sizes.h>
#ifndef __sizes_h #define SZ_48M (SZ_32M + SZ_16M)
#define __sizes_h 1
/* handy sizes */
#define SZ_16 0x00000010
#define SZ_32 0x00000020
#define SZ_64 0x00000040
#define SZ_128 0x00000080
#define SZ_256 0x00000100
#define SZ_512 0x00000200
#define SZ_1K 0x00000400
#define SZ_2K 0x00000800
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_32K 0x00008000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_48M 0x03000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define SZ_2G 0x80000000
#endif
/* END */
arch/arm/include/asm/smp.h
View file @ 4b60e5f9
...@@ -14,8 +14,6 @@ ...@@ -14,8 +14,6 @@
#include <linux/cpumask.h> #include <linux/cpumask.h>
#include <linux/thread_info.h> #include <linux/thread_info.h>
#include <mach/smp.h>
#ifndef CONFIG_SMP #ifndef CONFIG_SMP
# error "<asm/smp.h> included in non-SMP build" # error "<asm/smp.h> included in non-SMP build"
#endif #endif
...@@ -47,9 +45,9 @@ extern void smp_init_cpus(void); ...@@ -47,9 +45,9 @@ extern void smp_init_cpus(void);
/* /*
* Raise an IPI cross call on CPUs in callmap. * Provide a function to raise an IPI cross call on CPUs in callmap.
*/ */
extern void smp_cross_call(const struct cpumask *mask, int ipi); extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
/* /*
* Boot a secondary CPU, and assign it the specified idle task. * Boot a secondary CPU, and assign it the specified idle task.
......
arch/arm/kernel/smp.c
View file @ 4b60e5f9
...@@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus) ...@@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
} }
} }
static void (*smp_cross_call)(const struct cpumask *, unsigned int);
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
{
smp_cross_call = fn;
}
void arch_send_call_function_ipi_mask(const struct cpumask *mask) void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{ {
smp_cross_call(mask, IPI_CALL_FUNC); smp_cross_call(mask, IPI_CALL_FUNC);
......
arch/arm/mach-davinci/include/mach/memory.h
View file @ 4b60e5f9
...@@ -41,27 +41,11 @@ ...@@ -41,27 +41,11 @@
*/ */
#define CONSISTENT_DMA_SIZE (14<<20) #define CONSISTENT_DMA_SIZE (14<<20)
#ifndef __ASSEMBLY__
/* /*
* Restrict DMA-able region to workaround silicon bug. The bug * Restrict DMA-able region to workaround silicon bug. The bug
* restricts buffers available for DMA to video hardware to be * restricts buffers available for DMA to video hardware to be
* below 128M * below 128M
*/ */
static inline void #define ARM_DMA_ZONE_SIZE SZ_128M
__arch_adjust_zones(unsigned long *size, unsigned long *holes)
{
unsigned int sz = (128<<20) >> PAGE_SHIFT;
size[1] = size[0] - sz;
size[0] = sz;
}
#define arch_adjust_zones(zone_size, holes) \
if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
#endif
#endif /* __ASM_ARCH_MEMORY_H */ #endif /* __ASM_ARCH_MEMORY_H */
arch/arm/mach-exynos4/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
/* linux/arch/arm/mach-exynos4/include/mach/smp.h
*
* Cloned from arch/arm/mach-realview/include/mach/smp.h
*/
#ifndef ASM_ARCH_SMP_H
#define ASM_ARCH_SMP_H __FILE__
#include <asm/hardware/gic.h>
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-exynos4/platsmp.c
View file @ 4b60e5f9
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <asm/unified.h> #include <asm/unified.h>
...@@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
smp_cross_call(cpumask_of(cpu), 1); gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
...@@ -147,6 +148,8 @@ void __init smp_init_cpus(void) ...@@ -147,6 +148,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-h720x/include/mach/memory.h
View file @ 4b60e5f9
...@@ -13,7 +13,6 @@ ...@@ -13,7 +13,6 @@
* There should not be more than (0xd0000000 - 0xc0000000) * There should not be more than (0xd0000000 - 0xc0000000)
* bytes of RAM. * bytes of RAM.
*/ */
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) #define ARM_DMA_ZONE_SIZE SZ_256M
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
#endif #endif
arch/arm/mach-integrator/integrator_ap.c
View file @ 4b60e5f9
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <linux/clockchips.h> #include <linux/clockchips.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/platform.h> #include <mach/platform.h>
...@@ -43,7 +44,6 @@ ...@@ -43,7 +44,6 @@
#include <mach/lm.h> #include <mach/lm.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
...@@ -222,7 +222,7 @@ device_initcall(irq_syscore_init); ...@@ -222,7 +222,7 @@ device_initcall(irq_syscore_init);
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
static int ap_flash_init(void) static int ap_flash_init(struct platform_device *dev)
{ {
u32 tmp; u32 tmp;
...@@ -239,7 +239,7 @@ static int ap_flash_init(void) ...@@ -239,7 +239,7 @@ static int ap_flash_init(void)
return 0; return 0;
} }
static void ap_flash_exit(void) static void ap_flash_exit(struct platform_device *dev)
{ {
u32 tmp; u32 tmp;
...@@ -255,15 +255,14 @@ static void ap_flash_exit(void) ...@@ -255,15 +255,14 @@ static void ap_flash_exit(void)
} }
} }
static void ap_flash_set_vpp(int on) static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{ {
void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
} }
static struct flash_platform_data ap_flash_data = { static struct physmap_flash_data ap_flash_data = {
.map_name = "cfi_probe",
.width = 4, .width = 4,
.init = ap_flash_init, .init = ap_flash_init,
.exit = ap_flash_exit, .exit = ap_flash_exit,
...@@ -277,7 +276,7 @@ static struct resource cfi_flash_resource = { ...@@ -277,7 +276,7 @@ static struct resource cfi_flash_resource = {
}; };
static struct platform_device cfi_flash_device = { static struct platform_device cfi_flash_device = {
.name = "armflash", .name = "physmap-flash",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &ap_flash_data, .platform_data = &ap_flash_data,
......
arch/arm/mach-integrator/integrator_cp.c
View file @ 4b60e5f9
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/gfp.h> #include <linux/gfp.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/platform.h> #include <mach/platform.h>
...@@ -35,7 +36,6 @@ ...@@ -35,7 +36,6 @@
#include <mach/lm.h> #include <mach/lm.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
...@@ -246,7 +246,7 @@ static struct clk_lookup cp_lookups[] = { ...@@ -246,7 +246,7 @@ static struct clk_lookup cp_lookups[] = {
/* /*
* Flash handling. * Flash handling.
*/ */
static int intcp_flash_init(void) static int intcp_flash_init(struct platform_device *dev)
{ {
u32 val; u32 val;
...@@ -257,7 +257,7 @@ static int intcp_flash_init(void) ...@@ -257,7 +257,7 @@ static int intcp_flash_init(void)
return 0; return 0;
} }
static void intcp_flash_exit(void) static void intcp_flash_exit(struct platform_device *dev)
{ {
u32 val; u32 val;
...@@ -266,7 +266,7 @@ static void intcp_flash_exit(void) ...@@ -266,7 +266,7 @@ static void intcp_flash_exit(void)
writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
} }
static void intcp_flash_set_vpp(int on) static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{ {
u32 val; u32 val;
...@@ -278,8 +278,7 @@ static void intcp_flash_set_vpp(int on) ...@@ -278,8 +278,7 @@ static void intcp_flash_set_vpp(int on)
writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
} }
static struct flash_platform_data intcp_flash_data = { static struct physmap_flash_data intcp_flash_data = {
.map_name = "cfi_probe",
.width = 4, .width = 4,
.init = intcp_flash_init, .init = intcp_flash_init,
.exit = intcp_flash_exit, .exit = intcp_flash_exit,
...@@ -293,7 +292,7 @@ static struct resource intcp_flash_resource = { ...@@ -293,7 +292,7 @@ static struct resource intcp_flash_resource = {
}; };
static struct platform_device intcp_flash_device = { static struct platform_device intcp_flash_device = {
.name = "armflash", .name = "physmap-flash",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &intcp_flash_data, .platform_data = &intcp_flash_data,
......
arch/arm/mach-ixp4xx/common-pci.c
View file @ 4b60e5f9
...@@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) ...@@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
} }
/*
* Only first 64MB of memory can be accessed via PCI.
* We use GFP_DMA to allocate safe buffers to do map/unmap.
* This is really ugly and we need a better way of specifying
* DMA-capable regions of memory.
*/
void __init ixp4xx_adjust_zones(unsigned long *zone_size,
unsigned long *zhole_size)
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
/*
* Only adjust if > 64M on current system
*/
if (zone_size[0] <= sz)
return;
zone_size[1] = zone_size[0] - sz;
zone_size[0] = sz;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
}
void __init ixp4xx_pci_preinit(void) void __init ixp4xx_pci_preinit(void)
{ {
unsigned long cpuid = read_cpuid_id(); unsigned long cpuid = read_cpuid_id();
......
arch/arm/mach-ixp4xx/include/mach/memory.h
View file @ 4b60e5f9
...@@ -14,16 +14,8 @@ ...@@ -14,16 +14,8 @@
*/ */
#define PLAT_PHYS_OFFSET UL(0x00000000) #define PLAT_PHYS_OFFSET UL(0x00000000)
#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) #ifdef CONFIG_PCI
#define ARM_DMA_ZONE_SIZE SZ_64M
void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
#define arch_adjust_zones(size, holes) \
ixp4xx_adjust_zones(size, holes)
#define ISA_DMA_THRESHOLD (SZ_64M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
#endif #endif
#endif #endif
arch/arm/mach-msm/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_SMP_H
#define __ASM_ARCH_MSM_SMP_H
#include <asm/hardware/gic.h>
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-msm/platsmp.c
View file @ 4b60e5f9
...@@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
smp_cross_call(cpumask_of(cpu), 1); gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
...@@ -151,6 +151,8 @@ void __init smp_init_cpus(void) ...@@ -151,6 +151,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < NR_CPUS; i++) for (i = 0; i < NR_CPUS; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-mxs/Kconfig
View file @ 4b60e5f9
...@@ -17,6 +17,16 @@ config SOC_IMX28 ...@@ -17,6 +17,16 @@ config SOC_IMX28
comment "MXS platforms:" comment "MXS platforms:"
config MACH_STMP378X_DEVB
bool "Support STMP378x_devb Platform"
select SOC_IMX23
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_MXS_MMC
help
Include support for STMP378x-devb platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX23EVK config MACH_MX23EVK
bool "Support MX23EVK Platform" bool "Support MX23EVK Platform"
select SOC_IMX23 select SOC_IMX23
......
arch/arm/mach-mxs/Makefile
View file @ 4b60e5f9
...@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o ...@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
obj-$(CONFIG_MODULE_TX28) += module-tx28.o obj-$(CONFIG_MODULE_TX28) += module-tx28.o
......
arch/arm/mach-mxs/mach-stmp378x_devb.c 0 → 100644
View file @ 4b60e5f9
/*
* board setup for STMP378x-Development-Board
*
* based on mx23evk board setup and information gained form the original
* plat-stmp based board setup, now converted to mach-mxs.
*
* Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/iomux-mx23.h>
#include "devices-mx23.h"
#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30)
#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29)
#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
/* duart (extended setup missing in old boardcode, too */
MX23_PAD_PWM0__DUART_RX,
MX23_PAD_PWM1__DUART_TX,
/* auart */
MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
/* mmc */
MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX23_PAD_SSP1_CMD__SSP1_CMD |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX23_PAD_SSP1_DETECT__SSP1_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX23_PAD_SSP1_SCK__SSP1_SCK |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
};
static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
.wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
};
static struct spi_board_info spi_board_info[] __initdata = {
#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
{
.modalias = "enc28j60",
.max_speed_hz = 6 * 1000 * 1000,
.bus_num = 1,
.chip_select = 0,
.platform_data = NULL,
},
#endif
};
static void __init stmp378x_dvb_init(void)
{
int ret;
mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
ARRAY_SIZE(stmp378x_dvb_pads));
mx23_add_duart();
mx23_add_auart0();
/* power on mmc slot */
ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
if (ret)
pr_warn("could not power mmc (%d)\n", ret);
mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
}
static void __init stmp378x_dvb_timer_init(void)
{
mx23_clocks_init();
}
static struct sys_timer stmp378x_dvb_timer = {
.init = stmp378x_dvb_timer_init,
};
MACHINE_START(STMP378X, "STMP378X")
.map_io = mx23_map_io,
.init_irq = mx23_init_irq,
.init_machine = stmp378x_dvb_init,
.timer = &stmp378x_dvb_timer,
MACHINE_END
arch/arm/mach-omap1/flash.c
View file @ 4b60e5f9
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
#include <plat/tc.h> #include <plat/tc.h>
#include <plat/flash.h> #include <plat/flash.h>
void omap1_set_vpp(struct map_info *map, int enable) void omap1_set_vpp(struct platform_device *pdev, int enable)
{ {
static int count; static int count;
u32 l; u32 l;
......
arch/arm/mach-omap2/include/mach/omap4-common.h
View file @ 4b60e5f9
...@@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr; ...@@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr;
extern void __init gic_init_irq(void); extern void __init gic_init_irq(void);
extern void omap_smc1(u32 fn, u32 arg); extern void omap_smc1(u32 fn, u32 arg);
#ifdef CONFIG_SMP
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
#endif
#endif #endif
arch/arm/mach-omap2/omap-smp.c
View file @ 4b60e5f9
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/omap4-common.h> #include <mach/omap4-common.h>
...@@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
omap_modify_auxcoreboot0(0x200, 0xfffffdff); omap_modify_auxcoreboot0(0x200, 0xfffffdff);
flush_cache_all(); flush_cache_all();
smp_wmb(); smp_wmb();
smp_cross_call(cpumask_of(cpu), 1); gic_raise_softirq(cpumask_of(cpu), 1);
/* /*
* Now the secondary core is starting up let it run its * Now the secondary core is starting up let it run its
...@@ -118,6 +119,8 @@ void __init smp_init_cpus(void) ...@@ -118,6 +119,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-pxa/cm-x2xx-pci.c
View file @ 4b60e5f9
...@@ -29,33 +29,6 @@ ...@@ -29,33 +29,6 @@
unsigned long it8152_base_address; unsigned long it8152_base_address;
static int cmx2xx_it8152_irq_gpio; static int cmx2xx_it8152_irq_gpio;
/*
* Only first 64MB of memory can be accessed via PCI.
* We use GFP_DMA to allocate safe buffers to do map/unmap.
* This is really ugly and we need a better way of specifying
* DMA-capable regions of memory.
*/
void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
unsigned long *zhole_size)
{
unsigned int sz = SZ_64M >> PAGE_SHIFT;
if (machine_is_armcore()) {
pr_info("Adjusting zones for CM-X2XX\n");
/*
* Only adjust if > 64M on current system
*/
if (zone_size[0] <= sz)
return;
zone_size[1] = zone_size[0] - sz;
zone_size[0] = sz;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
}
}
static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{ {
/* clear our parent irq */ /* clear our parent irq */
......
arch/arm/mach-pxa/hx4700.c
View file @ 4b60e5f9
...@@ -735,7 +735,7 @@ static struct platform_device bq24022 = { ...@@ -735,7 +735,7 @@ static struct platform_device bq24022 = {
* StrataFlash * StrataFlash
*/ */
static void hx4700_set_vpp(struct map_info *map, int vpp) static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
{ {
gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp); gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
} }
......
arch/arm/mach-pxa/include/mach/memory.h
View file @ 4b60e5f9
...@@ -17,14 +17,8 @@ ...@@ -17,14 +17,8 @@
*/ */
#define PLAT_PHYS_OFFSET UL(0xa0000000) #define PLAT_PHYS_OFFSET UL(0xa0000000)
#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); #define ARM_DMA_ZONE_SIZE SZ_64M
#define arch_adjust_zones(size, holes) \
cmx2xx_pci_adjust_zones(size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
#endif #endif
#endif #endif
arch/arm/mach-pxa/magician.c
View file @ 4b60e5f9
...@@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = { ...@@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = {
* StrataFlash * StrataFlash
*/ */
static void magician_set_vpp(struct map_info *map, int vpp) static void magician_set_vpp(struct platform_device *pdev, int vpp)
{ {
gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
} }
......
arch/arm/mach-realview/core.c
View file @ 4b60e5f9
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <linux/amba/mmci.h> #include <linux/amba/mmci.h>
#include <linux/gfp.h> #include <linux/gfp.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/mtd/physmap.h>
#include <asm/system.h> #include <asm/system.h>
#include <mach/hardware.h> #include <mach/hardware.h>
...@@ -41,7 +42,6 @@ ...@@ -41,7 +42,6 @@
#include <asm/hardware/icst.h> #include <asm/hardware/icst.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
...@@ -56,48 +56,9 @@ ...@@ -56,48 +56,9 @@
#include "core.h" #include "core.h"
#ifdef CONFIG_ZONE_DMA
/*
* Adjust the zones if there are restrictions for DMA access.
*/
void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
{
unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
if (!machine_is_realview_pbx() || size[0] <= dma_size)
return;
size[ZONE_NORMAL] = size[0] - dma_size;
size[ZONE_DMA] = dma_size;
hole[ZONE_NORMAL] = hole[0];
hole[ZONE_DMA] = 0;
}
#endif
#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
static int realview_flash_init(void) static void realview_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
val = __raw_readl(REALVIEW_FLASHCTRL);
val &= ~REALVIEW_FLASHPROG_FLVPPEN;
__raw_writel(val, REALVIEW_FLASHCTRL);
return 0;
}
static void realview_flash_exit(void)
{
u32 val;
val = __raw_readl(REALVIEW_FLASHCTRL);
val &= ~REALVIEW_FLASHPROG_FLVPPEN;
__raw_writel(val, REALVIEW_FLASHCTRL);
}
static void realview_flash_set_vpp(int on)
{ {
u32 val; u32 val;
...@@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on) ...@@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on)
__raw_writel(val, REALVIEW_FLASHCTRL); __raw_writel(val, REALVIEW_FLASHCTRL);
} }
static struct flash_platform_data realview_flash_data = { static struct physmap_flash_data realview_flash_data = {
.map_name = "cfi_probe",
.width = 4, .width = 4,
.init = realview_flash_init,
.exit = realview_flash_exit,
.set_vpp = realview_flash_set_vpp, .set_vpp = realview_flash_set_vpp,
}; };
struct platform_device realview_flash_device = { struct platform_device realview_flash_device = {
.name = "armflash", .name = "physmap-flash",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &realview_flash_data, .platform_data = &realview_flash_data,
......
arch/arm/mach-realview/include/mach/memory.h
View file @ 4b60e5f9
...@@ -29,13 +29,8 @@ ...@@ -29,13 +29,8 @@
#define PLAT_PHYS_OFFSET UL(0x00000000) #define PLAT_PHYS_OFFSET UL(0x00000000)
#endif #endif
#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) #ifdef CONFIG_ZONE_DMA
extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); #define ARM_DMA_ZONE_SIZE SZ_256M
#define arch_adjust_zones(size, hole) \
realview_adjust_zones(size, hole)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
#endif #endif
#ifdef CONFIG_SPARSEMEM #ifdef CONFIG_SPARSEMEM
......
arch/arm/mach-realview/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-realview/platsmp.c
View file @ 4b60e5f9
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <asm/unified.h> #include <asm/unified.h>
...@@ -61,6 +62,8 @@ void __init smp_init_cpus(void) ...@@ -61,6 +62,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-s3c2410/nor-simtec.c
View file @ 4b60e5f9
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#include "nor-simtec.h" #include "nor-simtec.h"
static void simtec_nor_vpp(struct map_info *map, int vpp) static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
{ {
unsigned int val; unsigned int val;
unsigned long flags; unsigned long flags;
......
arch/arm/mach-sa1100/include/mach/memory.h
View file @ 4b60e5f9
...@@ -14,18 +14,8 @@ ...@@ -14,18 +14,8 @@
*/ */
#define PLAT_PHYS_OFFSET UL(0xc0000000) #define PLAT_PHYS_OFFSET UL(0xc0000000)
#ifndef __ASSEMBLY__
#ifdef CONFIG_SA1111 #ifdef CONFIG_SA1111
void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); #define ARM_DMA_ZONE_SIZE SZ_1M
#define arch_adjust_zones(size, holes) \
sa1111_adjust_zones(size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
#endif
#endif #endif
/* /*
......
arch/arm/mach-shark/include/mach/memory.h
View file @ 4b60e5f9
...@@ -17,25 +17,7 @@ ...@@ -17,25 +17,7 @@
*/ */
#define PLAT_PHYS_OFFSET UL(0x08000000) #define PLAT_PHYS_OFFSET UL(0x08000000)
#ifndef __ASSEMBLY__ #define ARM_DMA_ZONE_SIZE SZ_4M
static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
{
/* Only the first 4 MB (=1024 Pages) are usable for DMA */
/* See dev / -> .properties in OpenFirmware. */
zone_size[1] = zone_size[0] - 1024;
zone_size[0] = 1024;
zhole_size[1] = zhole_size[0];
zhole_size[0] = 0;
}
#define arch_adjust_zones(size, holes) \
__arch_adjust_zones(size, holes)
#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
#endif
/* /*
* Cache flushing area * Cache flushing area
......
arch/arm/mach-shmobile/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
#ifndef __MACH_SMP_H
#define __MACH_SMP_H
#include <asm/hardware/gic.h>
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
#if defined(CONFIG_ARM_GIC)
gic_raise_softirq(mask, ipi);
#endif
}
#endif
arch/arm/mach-shmobile/platsmp.c
View file @ 4b60e5f9
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/smp.h> #include <linux/smp.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/hardware/gic.h>
#include <asm/localtimer.h> #include <asm/localtimer.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <mach/common.h> #include <mach/common.h>
...@@ -57,6 +58,8 @@ void __init smp_init_cpus(void) ...@@ -57,6 +58,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-stmp378x/Makefile deleted 100644 → 0
View file @ e8765afe
obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
arch/arm/mach-stmp378x/Makefile.boot deleted 100644 → 0
View file @ e8765afe
zreladdr-y := 0x40008000
params_phys-y := 0x40000100
initrd_phys-y := 0x40800000
arch/arm/mach-stmp378x/include/mach/entry-macro.S deleted 100644 → 0
View file @ e8765afe
/*
* Low-level IRQ helper macros for Freescale STMP378X
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #0xf0000000 @ vm address of IRQ controller
ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
cmp \irqnr, #0x7f
moveqs \irqnr, #0 @ Zero flag set for no IRQ
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
arch/arm/mach-stmp378x/include/mach/irqs.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP378X interrupts
*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define IRQ_DEBUG_UART 0
#define IRQ_COMMS_RX 1
#define IRQ_COMMS_TX 1
#define IRQ_SSP2_ERROR 2
#define IRQ_VDD5V 3
#define IRQ_HEADPHONE_SHORT 4
#define IRQ_DAC_DMA 5
#define IRQ_DAC_ERROR 6
#define IRQ_ADC_DMA 7
#define IRQ_ADC_ERROR 8
#define IRQ_SPDIF_DMA 9
#define IRQ_SAIF2_DMA 9
#define IRQ_SPDIF_ERROR 10
#define IRQ_SAIF1_IRQ 10
#define IRQ_SAIF2_IRQ 10
#define IRQ_USB_CTRL 11
#define IRQ_USB_WAKEUP 12
#define IRQ_GPMI_DMA 13
#define IRQ_SSP1_DMA 14
#define IRQ_SSP_ERROR 15
#define IRQ_GPIO0 16
#define IRQ_GPIO1 17
#define IRQ_GPIO2 18
#define IRQ_SAIF1_DMA 19
#define IRQ_SSP2_DMA 20
#define IRQ_ECC8_IRQ 21
#define IRQ_RTC_ALARM 22
#define IRQ_UARTAPP_TX_DMA 23
#define IRQ_UARTAPP_INTERNAL 24
#define IRQ_UARTAPP_RX_DMA 25
#define IRQ_I2C_DMA 26
#define IRQ_I2C_ERROR 27
#define IRQ_TIMER0 28
#define IRQ_TIMER1 29
#define IRQ_TIMER2 30
#define IRQ_TIMER3 31
#define IRQ_BATT_BRNOUT 32
#define IRQ_VDDD_BRNOUT 33
#define IRQ_VDDIO_BRNOUT 34
#define IRQ_VDD18_BRNOUT 35
#define IRQ_TOUCH_DETECT 36
#define IRQ_LRADC_CH0 37
#define IRQ_LRADC_CH1 38
#define IRQ_LRADC_CH2 39
#define IRQ_LRADC_CH3 40
#define IRQ_LRADC_CH4 41
#define IRQ_LRADC_CH5 42
#define IRQ_LRADC_CH6 43
#define IRQ_LRADC_CH7 44
#define IRQ_LCDIF_DMA 45
#define IRQ_LCDIF_ERROR 46
#define IRQ_DIGCTL_DEBUG_TRAP 47
#define IRQ_RTC_1MSEC 48
#define IRQ_DRI_DMA 49
#define IRQ_DRI_ATTENTION 50
#define IRQ_GPMI_ATTENTION 51
#define IRQ_IR 52
#define IRQ_DCP_VMI 53
#define IRQ_DCP 54
#define IRQ_BCH 56
#define IRQ_PXP 57
#define IRQ_UARTAPP2_TX_DMA 58
#define IRQ_UARTAPP2_INTERNAL 59
#define IRQ_UARTAPP2_RX_DMA 60
#define IRQ_VDAC_DETECT 61
#define IRQ_VDD5V_DROOP 64
#define IRQ_DCDC4P2_BO 65
#define NR_REAL_IRQS 128
#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
/* All interrupts are FIQ capable */
#define FIQ_START IRQ_DEBUG_UART
/* Hard disk IRQ is a GPMI attention IRQ */
#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
arch/arm/mach-stmp378x/include/mach/pins.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP378X SoC pin multiplexing
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_PINS_H
#define __ASM_ARCH_PINS_H
/*
* Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
* interface this pin belongs to.
*/
/* Bank 0 */
#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
/* Bank 1 */
#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
#define PINID_PWM0 STMP3XXX_PINID(1, 26)
#define PINID_PWM1 STMP3XXX_PINID(1, 27)
#define PINID_PWM2 STMP3XXX_PINID(1, 28)
#define PINID_PWM3 STMP3XXX_PINID(1, 29)
#define PINID_PWM4 STMP3XXX_PINID(1, 30)
/* Bank 2 */
#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
/* Bank 3 */
#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
#endif /* __ASM_ARCH_PINS_H */
arch/arm/mach-stmp378x/include/mach/regs-apbh.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: APBH register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_APBH
#define _MACH_REGS_APBH
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
#define REGS_APBH_PHYS 0x80004000
#define REGS_APBH_SIZE 0x2000
#define HW_APBH_CTRL0 0x0
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define BM_APBH_CTRL0_CLKGATE 0x40000000
#define BM_APBH_CTRL0_SFTRST 0x80000000
#define HW_APBH_CTRL1 0x10
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
#define HW_APBH_CTRL2 0x20
#define HW_APBH_DEVSEL 0x30
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
#define HW_APBH_CHn_NXTCMDAR 0x50
#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
#define BM_APBH_CHn_CMD_COMMAND 0x00000003
#define BP_APBH_CHn_CMD_COMMAND 0
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBH_CHn_CMD_CMDWORDS 12
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBH_CHn_CMD_XFER_COUNT 16
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
#define HW_APBH_CHn_SEMA 0x80
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBH_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp378x/include/mach/regs-apbx.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: APBX register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_APBX
#define _MACH_REGS_APBX
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
#define REGS_APBX_PHYS 0x80024000
#define REGS_APBX_SIZE 0x2000
#define HW_APBX_CTRL0 0x0
#define BM_APBX_CTRL0_CLKGATE 0x40000000
#define BM_APBX_CTRL0_SFTRST 0x80000000
#define HW_APBX_CTRL1 0x10
#define HW_APBX_CTRL2 0x20
#define HW_APBX_CHANNEL_CTRL 0x30
#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
#define HW_APBX_DEVSEL 0x40
#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
#define HW_APBX_CHn_NXTCMDAR 0x110
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
#define BP_APBX_CHn_CMD_COMMAND 0
#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBX_CHn_CMD_CMDWORDS 12
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBX_CHn_CMD_XFER_COUNT 16
#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
#define HW_APBX_CHn_BAR 0x130
#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
#define HW_APBX_CHn_SEMA 0x140
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBX_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp378x/include/mach/regs-audioin.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: AUDIOIN register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
#define REGS_AUDIOIN_PHYS 0x8004C000
#define REGS_AUDIOIN_SIZE 0x2000
#define HW_AUDIOIN_CTRL 0x0
#define BM_AUDIOIN_CTRL_RUN 0x00000001
#define BP_AUDIOIN_CTRL_RUN 0
#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
#define HW_AUDIOIN_STAT 0x10
#define HW_AUDIOIN_ADCSRR 0x20
#define HW_AUDIOIN_ADCVOLUME 0x30
#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
#define HW_AUDIOIN_ADCDEBUG 0x40
#define HW_AUDIOIN_ADCVOL 0x50
#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
#define HW_AUDIOIN_MICLINE 0x60
#define HW_AUDIOIN_ANACLKCTRL 0x70
#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
#define HW_AUDIOIN_DATA 0x80
arch/arm/mach-stmp378x/include/mach/regs-audioout.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: AUDIOOUT register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
#define REGS_AUDIOOUT_PHYS 0x80048000
#define REGS_AUDIOOUT_SIZE 0x2000
#define HW_AUDIOOUT_CTRL 0x0
#define BM_AUDIOOUT_CTRL_RUN 0x00000001
#define BP_AUDIOOUT_CTRL_RUN 0
#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
#define HW_AUDIOOUT_STAT 0x10
#define HW_AUDIOOUT_DACSRR 0x20
#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
#define BP_AUDIOOUT_DACSRR_SRC_INT 16
#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
#define BP_AUDIOOUT_DACSRR_BASEMULT 28
#define HW_AUDIOOUT_DACVOLUME 0x30
#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
#define HW_AUDIOOUT_DACDEBUG 0x40
#define HW_AUDIOOUT_HPVOL 0x50
#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
#define HW_AUDIOOUT_PWRDN 0x70
#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
#define HW_AUDIOOUT_REFCTRL 0x80
#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
#define HW_AUDIOOUT_ANACTRL 0x90
#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
#define HW_AUDIOOUT_TEST 0xA0
#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
#define HW_AUDIOOUT_BISTCTRL 0xB0
#define HW_AUDIOOUT_BISTSTAT0 0xC0
#define HW_AUDIOOUT_BISTSTAT1 0xD0
#define HW_AUDIOOUT_ANACLKCTRL 0xE0
#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
#define HW_AUDIOOUT_DATA 0xF0
#define HW_AUDIOOUT_SPEAKERCTRL 0x100
#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
#define HW_AUDIOOUT_VERSION 0x200
arch/arm/mach-stmp378x/include/mach/regs-bch.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: BCH register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
#define REGS_BCH_PHYS 0x8000A000
#define REGS_BCH_SIZE 0x2000
#define HW_BCH_CTRL 0x0
#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
#define BP_BCH_CTRL_COMPLETE_IRQ 0
#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
#define HW_BCH_STATUS0 0x10
#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
#define BM_BCH_STATUS0_CORRECTED 0x00000008
#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
#define BP_BCH_STATUS0_STATUS_BLK0 8
#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
#define BP_BCH_STATUS0_COMPLETED_CE 16
#define HW_BCH_LAYOUTSELECT 0x70
#define HW_BCH_FLASH0LAYOUT0 0x80
#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
#define BP_BCH_FLASH0LAYOUT0_ECC0 12
#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
#define BP_BCH_FLASH0LAYOUT1_ECCN 12
#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
#define HW_BCH_BLOCKNAME 0x150
arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: CLKCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_CLKCTRL
#define _MACH_REGS_CLKCTRL
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
#define REGS_CLKCTRL_PHYS 0x80040000
#define REGS_CLKCTRL_SIZE 0x2000
#define HW_CLKCTRL_PLLCTRL0 0x0
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
#define HW_CLKCTRL_CPU 0x20
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
#define BP_CLKCTRL_CPU_DIV_CPU 0
#define HW_CLKCTRL_HBUS 0x30
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
#define BP_CLKCTRL_HBUS_DIV 0
#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
#define HW_CLKCTRL_XBUS 0x40
#define HW_CLKCTRL_XTAL 0x50
#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
#define HW_CLKCTRL_PIX 0x60
#define BM_CLKCTRL_PIX_DIV 0x00000FFF
#define BP_CLKCTRL_PIX_DIV 0
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
#define HW_CLKCTRL_SSP 0x70
#define HW_CLKCTRL_GPMI 0x80
#define HW_CLKCTRL_SPDIF 0x90
#define HW_CLKCTRL_EMI 0xA0
#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
#define BP_CLKCTRL_EMI_DIV_EMI 0
#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
#define HW_CLKCTRL_IR 0xB0
#define HW_CLKCTRL_SAIF 0xC0
#define HW_CLKCTRL_TV 0xD0
#define HW_CLKCTRL_ETM 0xE0
#define HW_CLKCTRL_FRAC 0xF0
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
#define BP_CLKCTRL_FRAC_EMIFRAC 8
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
#define BP_CLKCTRL_FRAC_PIXFRAC 16
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
#define HW_CLKCTRL_FRAC1 0x100
#define HW_CLKCTRL_CLKSEQ 0x110
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
#define HW_CLKCTRL_RESET 0x120
#define BM_CLKCTRL_RESET_DIG 0x00000001
#define BP_CLKCTRL_RESET_DIG 0
#endif
arch/arm/mach-stmp378x/include/mach/regs-dcp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: DCP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
#define REGS_DCP_PHYS 0x80028000
#define REGS_DCP_SIZE 0x2000
#define HW_DCP_CTRL 0x0
#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
#define BM_DCP_CTRL_CLKGATE 0x40000000
#define BM_DCP_CTRL_SFTRST 0x80000000
#define HW_DCP_STAT 0x10
#define BM_DCP_STAT_IRQ 0x0000000F
#define BP_DCP_STAT_IRQ 0
#define HW_DCP_CHANNELCTRL 0x20
#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
#define HW_DCP_CONTEXT 0x50
#define BM_DCP_PACKET1_INTERRUPT 0x00000001
#define BP_DCP_PACKET1_INTERRUPT 0
#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
#define BM_DCP_PACKET1_CHAIN 0x00000004
#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
#define BM_DCP_PACKET1_OTP_KEY 0x00000400
#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
#define BM_DCP_PACKET1_HASH_INIT 0x00001000
#define BM_DCP_PACKET1_HASH_TERM 0x00002000
#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
#define BP_DCP_PACKET2_CIPHER_SELECT 0
#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
#define BP_DCP_PACKET2_CIPHER_MODE 4
#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
#define BP_DCP_PACKET2_KEY_SELECT 8
#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
#define BP_DCP_PACKET2_HASH_SELECT 16
#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
#define BP_DCP_PACKET2_CIPHER_CFG 24
#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
#define HW_DCP_CHnCMDPTR 0x100
#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
#define HW_DCP_CHnSEMA 0x110
#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
#define BP_DCP_CHnSEMA_INCREMENT 0
#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
#define HW_DCP_CHnSTAT 0x120
arch/arm/mach-stmp378x/include/mach/regs-digctl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: DIGCTL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
#define REGS_DIGCTL_PHYS 0x8001C000
#define REGS_DIGCTL_SIZE 0x2000
#define HW_DIGCTL_CTRL 0x0
#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
#define HW_DIGCTL_ARMCACHE 0x2B0
#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
#define BP_DIGCTL_ARMCACHE_VALID_SS 16
arch/arm/mach-stmp378x/include/mach/regs-dram.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: DRAM register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
#define REGS_DRAM_PHYS 0x800E0000
#define REGS_DRAM_SIZE 0x2000
#define HW_DRAM_CTL06 0x18
#define HW_DRAM_CTL08 0x20
arch/arm/mach-stmp378x/include/mach/regs-dri.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: DRI register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
#define REGS_DRI_PHYS 0x80074000
#define REGS_DRI_SIZE 0x2000
#define HW_DRI_CTRL 0x0
#define BM_DRI_CTRL_RUN 0x00000001
#define BP_DRI_CTRL_RUN 0
#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
#define BM_DRI_CTRL_CLKGATE 0x40000000
#define BM_DRI_CTRL_SFTRST 0x80000000
#define HW_DRI_TIMING 0x10
#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
#define BP_DRI_TIMING_PILOT_REP_RATE 16
arch/arm/mach-stmp378x/include/mach/regs-ecc8.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: ECC8 register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
#define REGS_ECC8_PHYS 0x80008000
#define REGS_ECC8_SIZE 0x2000
#define HW_ECC8_CTRL 0x0
#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
#define BP_ECC8_CTRL_COMPLETE_IRQ 0
#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
#define HW_ECC8_STATUS0 0x10
#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
#define BM_ECC8_STATUS0_CORRECTED 0x00000008
#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
#define BP_ECC8_STATUS0_STATUS_AUX 8
#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
#define BP_ECC8_STATUS0_COMPLETED_CE 16
#define HW_ECC8_STATUS1 0x20
arch/arm/mach-stmp378x/include/mach/regs-emi.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: EMI register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
#define REGS_EMI_PHYS 0x80020000
#define REGS_EMI_SIZE 0x2000
#define HW_EMI_STAT 0x10
arch/arm/mach-stmp378x/include/mach/regs-gpmi.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: GPMI register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
#define REGS_GPMI_PHYS 0x8000C000
#define REGS_GPMI_SIZE 0x2000
#define HW_GPMI_CTRL0 0x0
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_GPMI_CTRL0_XFER_COUNT 0
#define BM_GPMI_CTRL0_CS 0x00300000
#define BP_GPMI_CTRL0_CS 20
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
#define BP_GPMI_CTRL0_ADDRESS 17
#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
#define BP_GPMI_CTRL0_COMMAND_MODE 24
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
#define BM_GPMI_CTRL0_RUN 0x20000000
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
#define BM_GPMI_CTRL0_SFTRST 0x80000000
#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
#define BP_GPMI_ECCCTRL_ECC_CMD 13
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
#define HW_GPMI_CTRL1 0x60
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
#define BP_GPMI_CTRL1_GPMI_MODE 0
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
#define BP_GPMI_CTRL1_RDN_DELAY 12
#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
#define HW_GPMI_TIMING0 0x70
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
#define BP_GPMI_TIMING0_DATA_SETUP 0
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
#define BP_GPMI_TIMING0_DATA_HOLD 8
#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
#define HW_GPMI_TIMING1 0x80
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
arch/arm/mach-stmp378x/include/mach/regs-i2c.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: I2C register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
#define REGS_I2C_PHYS 0x80058000
#define REGS_I2C_SIZE 0x2000
#define HW_I2C_CTRL0 0x0
#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_I2C_CTRL0_XFER_COUNT 0
#define BM_I2C_CTRL0_DIRECTION 0x00010000
#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
#define BM_I2C_CTRL0_CLKGATE 0x40000000
#define BM_I2C_CTRL0_SFTRST 0x80000000
#define HW_I2C_TIMING0 0x10
#define HW_I2C_TIMING1 0x20
#define HW_I2C_TIMING2 0x30
#define HW_I2C_CTRL1 0x40
#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
#define BP_I2C_CTRL1_SLAVE_IRQ 0
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
#define HW_I2C_VERSION 0x90
arch/arm/mach-stmp378x/include/mach/regs-icoll.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: ICOLL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_ICOLL
#define _MACH_REGS_ICOLL
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
#define REGS_ICOLL_PHYS 0x80000000
#define REGS_ICOLL_SIZE 0x2000
#define HW_ICOLL_VECTOR 0x0
#define HW_ICOLL_LEVELACK 0x10
#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
#define HW_ICOLL_CTRL 0x20
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
#define BM_ICOLL_CTRL_SFTRST 0x80000000
#define HW_ICOLL_STAT 0x70
#define HW_ICOLL_INTERRUPTn 0x120
#define HW_ICOLL_INTERRUPTn 0x120
#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
#endif
arch/arm/mach-stmp378x/include/mach/regs-ir.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: IR register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
#define REGS_IR_PHYS 0x80078000
#define REGS_IR_SIZE 0x2000
arch/arm/mach-stmp378x/include/mach/regs-lcdif.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: LCDIF register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
#define REGS_LCDIF_PHYS 0x80030000
#define REGS_LCDIF_SIZE 0x2000
#define HW_LCDIF_CTRL 0x0
#define BM_LCDIF_CTRL_RUN 0x00000001
#define BP_LCDIF_CTRL_RUN 0
#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
#define BP_LCDIF_CTRL_WORD_LENGTH 8
#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
#define BM_LCDIF_CTRL_SFTRST 0x80000000
#define HW_LCDIF_CTRL1 0x10
#define BM_LCDIF_CTRL1_RESET 0x00000001
#define BP_LCDIF_CTRL1_RESET 0
#define BM_LCDIF_CTRL1_MODE86 0x00000002
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
#define HW_LCDIF_TRANSFER_COUNT 0x20
#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
#define HW_LCDIF_CUR_BUF 0x30
#define HW_LCDIF_NEXT_BUF 0x40
#define HW_LCDIF_TIMING 0x60
#define HW_LCDIF_VDCTRL0 0x70
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
#define HW_LCDIF_VDCTRL1 0x80
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
#define HW_LCDIF_VDCTRL2 0x90
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
#define HW_LCDIF_VDCTRL3 0xA0
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
#define HW_LCDIF_VDCTRL4 0xB0
#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
#define HW_LCDIF_DVICTRL0 0xC0
#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
#define HW_LCDIF_DVICTRL1 0xD0
#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
#define HW_LCDIF_DVICTRL2 0xE0
#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
#define HW_LCDIF_DVICTRL3 0xF0
#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
#define HW_LCDIF_DVICTRL4 0x100
#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
#define HW_LCDIF_CSC_COEFF0 0x110
#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
#define BP_LCDIF_CSC_COEFF0_C0 16
#define HW_LCDIF_CSC_COEFF1 0x120
#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
#define BP_LCDIF_CSC_COEFF1_C1 0
#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
#define BP_LCDIF_CSC_COEFF1_C2 16
#define HW_LCDIF_CSC_COEFF2 0x130
#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
#define BP_LCDIF_CSC_COEFF2_C3 0
#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
#define BP_LCDIF_CSC_COEFF2_C4 16
#define HW_LCDIF_CSC_COEFF3 0x140
#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
#define BP_LCDIF_CSC_COEFF3_C5 0
#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
#define BP_LCDIF_CSC_COEFF3_C6 16
#define HW_LCDIF_CSC_COEFF4 0x150
#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
#define BP_LCDIF_CSC_COEFF4_C7 0
#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
#define BP_LCDIF_CSC_COEFF4_C8 16
#define HW_LCDIF_CSC_OFFSET 0x160
#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
#define HW_LCDIF_CSC_LIMIT 0x170
#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
#define HW_LCDIF_STAT 0x1D0
#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
arch/arm/mach-stmp378x/include/mach/regs-lradc.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: LRADC register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
#define REGS_LRADC_PHYS 0x80050000
#define REGS_LRADC_SIZE 0x2000
#define HW_LRADC_CTRL0 0x0
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
#define BP_LRADC_CTRL0_SCHEDULE 0
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
#define BM_LRADC_CTRL0_SFTRST 0x80000000
#define HW_LRADC_CTRL1 0x10
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
#define HW_LRADC_CTRL2 0x20
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
#define HW_LRADC_CTRL3 0x30
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
#define BP_LRADC_CTRL3_CYCLE_TIME 8
#define HW_LRADC_STATUS 0x40
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
#define HW_LRADC_CHn 0x50
#define BM_LRADC_CHn_VALUE 0x0003FFFF
#define BP_LRADC_CHn_VALUE 0
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
#define BP_LRADC_CHn_NUM_SAMPLES 24
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
#define HW_LRADC_DELAYn 0xD0
#define BM_LRADC_DELAYn_DELAY 0x000007FF
#define BP_LRADC_DELAYn_DELAY 0
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
#define BP_LRADC_DELAYn_LOOP_COUNT 11
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
#define BM_LRADC_DELAYn_KICK 0x00100000
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
#define HW_LRADC_CTRL4 0x140
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
#define BP_LRADC_CTRL4_LRADC6SELECT 24
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
#define BP_LRADC_CTRL4_LRADC7SELECT 28
arch/arm/mach-stmp378x/include/mach/regs-ocotp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: OCOTP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
#define REGS_OCOTP_PHYS 0x8002C000
#define REGS_OCOTP_SIZE 0x2000
#define HW_OCOTP_CTRL 0x0
#define BM_OCOTP_CTRL_BUSY 0x00000100
#define BM_OCOTP_CTRL_ERROR 0x00000200
#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
#define BP_OCOTP_CTRL_WR_UNLOCK 16
#define HW_OCOTP_DATA 0x10
#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
#define HW_OCOTP_CUSTn 0x20
arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: PINCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_PINCTRL
#define _MACH_REGS_PINCTRL
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
#define REGS_PINCTRL_PHYS 0x80018000
#define REGS_PINCTRL_SIZE 0x2000
#define HW_PINCTRL_MUXSEL0 0x100
#define HW_PINCTRL_MUXSEL1 0x110
#define HW_PINCTRL_MUXSEL2 0x120
#define HW_PINCTRL_MUXSEL3 0x130
#define HW_PINCTRL_MUXSEL4 0x140
#define HW_PINCTRL_MUXSEL5 0x150
#define HW_PINCTRL_MUXSEL6 0x160
#define HW_PINCTRL_MUXSEL7 0x170
#define HW_PINCTRL_DRIVE0 0x200
#define HW_PINCTRL_DRIVE1 0x210
#define HW_PINCTRL_DRIVE2 0x220
#define HW_PINCTRL_DRIVE3 0x230
#define HW_PINCTRL_DRIVE4 0x240
#define HW_PINCTRL_DRIVE5 0x250
#define HW_PINCTRL_DRIVE6 0x260
#define HW_PINCTRL_DRIVE7 0x270
#define HW_PINCTRL_DRIVE8 0x280
#define HW_PINCTRL_DRIVE9 0x290
#define HW_PINCTRL_DRIVE10 0x2A0
#define HW_PINCTRL_DRIVE11 0x2B0
#define HW_PINCTRL_DRIVE12 0x2C0
#define HW_PINCTRL_DRIVE13 0x2D0
#define HW_PINCTRL_DRIVE14 0x2E0
#define HW_PINCTRL_PULL0 0x400
#define HW_PINCTRL_PULL1 0x410
#define HW_PINCTRL_PULL2 0x420
#define HW_PINCTRL_PULL3 0x430
#define HW_PINCTRL_DOUT0 0x500
#define HW_PINCTRL_DOUT1 0x510
#define HW_PINCTRL_DOUT2 0x520
#define HW_PINCTRL_DIN0 0x600
#define HW_PINCTRL_DIN1 0x610
#define HW_PINCTRL_DIN2 0x620
#define HW_PINCTRL_DOE0 0x700
#define HW_PINCTRL_DOE1 0x710
#define HW_PINCTRL_DOE2 0x720
#define HW_PINCTRL_PIN2IRQ0 0x800
#define HW_PINCTRL_PIN2IRQ1 0x810
#define HW_PINCTRL_PIN2IRQ2 0x820
#define HW_PINCTRL_IRQEN0 0x900
#define HW_PINCTRL_IRQEN1 0x910
#define HW_PINCTRL_IRQEN2 0x920
#define HW_PINCTRL_IRQLEVEL0 0xA00
#define HW_PINCTRL_IRQLEVEL1 0xA10
#define HW_PINCTRL_IRQLEVEL2 0xA20
#define HW_PINCTRL_IRQPOL0 0xB00
#define HW_PINCTRL_IRQPOL1 0xB10
#define HW_PINCTRL_IRQPOL2 0xB20
#define HW_PINCTRL_IRQSTAT0 0xC00
#define HW_PINCTRL_IRQSTAT1 0xC10
#define HW_PINCTRL_IRQSTAT2 0xC20
#endif
arch/arm/mach-stmp378x/include/mach/regs-power.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: POWER register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_POWER
#define _MACH_REGS_POWER
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
#define REGS_POWER_PHYS 0x80044000
#define REGS_POWER_SIZE 0x2000
#define HW_POWER_CTRL 0x0
#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
#define BM_POWER_CTRL_CLKGATE 0x40000000
#define HW_POWER_5VCTRL 0x10
#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
#define HW_POWER_MINPWR 0x20
#define HW_POWER_CHARGE 0x30
#define HW_POWER_VDDDCTRL 0x40
#define HW_POWER_VDDACTRL 0x50
#define HW_POWER_VDDIOCTRL 0x60
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
#define BP_POWER_VDDIOCTRL_TRG 0
#define HW_POWER_STS 0xC0
#define BM_POWER_STS_VBUSVALID 0x00000002
#define BM_POWER_STS_BVALID 0x00000004
#define BM_POWER_STS_AVALID 0x00000008
#define BM_POWER_STS_DC_OK 0x00000200
#define HW_POWER_RESET 0x100
#define HW_POWER_DEBUG 0x110
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
#endif
arch/arm/mach-stmp378x/include/mach/regs-pwm.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: PWM register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
#define REGS_PWM_PHYS 0x80064000
#define REGS_PWM_SIZE 0x2000
#define HW_PWM_CTRL 0x0
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
#define HW_PWM_ACTIVEn 0x10
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
#define BP_PWM_ACTIVEn_ACTIVE 0
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
#define BP_PWM_ACTIVEn_INACTIVE 16
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
#define HW_PWM_PERIODn 0x20
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
#define BP_PWM_PERIODn_PERIOD 0
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
#define BP_PWM_PERIODn_ACTIVE_STATE 16
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
#define BP_PWM_PERIODn_INACTIVE_STATE 18
#define BM_PWM_PERIODn_CDIV 0x00700000
#define BP_PWM_PERIODn_CDIV 20
arch/arm/mach-stmp378x/include/mach/regs-pxp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: PXP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
#define REGS_PXP_PHYS 0x8002A000
#define REGS_PXP_SIZE 0x2000
#define HW_PXP_CTRL 0x0
#define BM_PXP_CTRL_ENABLE 0x00000001
#define BP_PXP_CTRL_ENABLE 0
#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
#define BM_PXP_CTRL_ROTATE 0x00000300
#define BP_PXP_CTRL_ROTATE 8
#define BM_PXP_CTRL_HFLIP 0x00000400
#define BM_PXP_CTRL_VFLIP 0x00000800
#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
#define BP_PXP_CTRL_S0_FORMAT 12
#define BM_PXP_CTRL_SCALE 0x00040000
#define BM_PXP_CTRL_CROP 0x00080000
#define HW_PXP_STAT 0x10
#define BM_PXP_STAT_IRQ 0x00000001
#define BP_PXP_STAT_IRQ 0
#define HW_PXP_RGBBUF 0x20
#define HW_PXP_RGBSIZE 0x40
#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
#define BP_PXP_RGBSIZE_HEIGHT 0
#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
#define BP_PXP_RGBSIZE_WIDTH 12
#define HW_PXP_S0BUF 0x50
#define HW_PXP_S0UBUF 0x60
#define HW_PXP_S0VBUF 0x70
#define HW_PXP_S0PARAM 0x80
#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
#define BP_PXP_S0PARAM_HEIGHT 0
#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
#define BP_PXP_S0PARAM_WIDTH 8
#define BM_PXP_S0PARAM_YBASE 0x00FF0000
#define BP_PXP_S0PARAM_YBASE 16
#define BM_PXP_S0PARAM_XBASE 0xFF000000
#define BP_PXP_S0PARAM_XBASE 24
#define HW_PXP_S0BACKGROUND 0x90
#define HW_PXP_S0CROP 0xA0
#define BM_PXP_S0CROP_HEIGHT 0x000000FF
#define BP_PXP_S0CROP_HEIGHT 0
#define BM_PXP_S0CROP_WIDTH 0x0000FF00
#define BP_PXP_S0CROP_WIDTH 8
#define BM_PXP_S0CROP_YBASE 0x00FF0000
#define BP_PXP_S0CROP_YBASE 16
#define BM_PXP_S0CROP_XBASE 0xFF000000
#define BP_PXP_S0CROP_XBASE 24
#define HW_PXP_S0SCALE 0xB0
#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
#define BP_PXP_S0SCALE_XSCALE 0
#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
#define BP_PXP_S0SCALE_YSCALE 16
#define HW_PXP_CSCCOEFF0 0xD0
#define HW_PXP_CSCCOEFF1 0xE0
#define HW_PXP_CSCCOEFF2 0xF0
#define HW_PXP_S0COLORKEYLOW 0x180
#define HW_PXP_S0COLORKEYHIGH 0x190
#define HW_PXP_OL0 (0x200 + 0 * 0x40)
#define HW_PXP_OL1 (0x200 + 1 * 0x40)
#define HW_PXP_OL2 (0x200 + 2 * 0x40)
#define HW_PXP_OL3 (0x200 + 3 * 0x40)
#define HW_PXP_OL4 (0x200 + 4 * 0x40)
#define HW_PXP_OL5 (0x200 + 5 * 0x40)
#define HW_PXP_OL6 (0x200 + 6 * 0x40)
#define HW_PXP_OL7 (0x200 + 7 * 0x40)
#define HW_PXP_OLn 0x200
#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
#define HW_PXP_OLnSIZE 0x210
#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
#define BP_PXP_OLnSIZE_HEIGHT 0
#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
#define BP_PXP_OLnSIZE_WIDTH 8
#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
#define HW_PXP_OLnPARAM 0x220
#define BM_PXP_OLnPARAM_ENABLE 0x00000001
#define BP_PXP_OLnPARAM_ENABLE 0
#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
#define BP_PXP_OLnPARAM_FORMAT 4
#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
#define BP_PXP_OLnPARAM_ALPHA 8
arch/arm/mach-stmp378x/include/mach/regs-rtc.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: RTC register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
#define REGS_RTC_PHYS 0x8005C000
#define REGS_RTC_SIZE 0x2000
#define HW_RTC_CTRL 0x0
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
#define HW_RTC_STAT 0x10
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
#define BP_RTC_STAT_NEW_REGS 8
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
#define BP_RTC_STAT_STALE_REGS 16
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
#define HW_RTC_SECONDS 0x30
#define HW_RTC_ALARM 0x40
#define HW_RTC_WATCHDOG 0x50
#define HW_RTC_PERSISTENT0 0x60
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
#define HW_RTC_PERSISTENT1 0x70
#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
#define BP_RTC_PERSISTENT1_GENERAL 0
#define HW_RTC_VERSION 0xD0
arch/arm/mach-stmp378x/include/mach/regs-saif.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: SAIF register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_SAIF_SIZE 0x2000
arch/arm/mach-stmp378x/include/mach/regs-spdif.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: SPDIF register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
#define REGS_SPDIF_PHYS 0x80054000
#define REGS_SPDIF_SIZE 0x2000
#define HW_SPDIF_CTRL 0x0
#define BM_SPDIF_CTRL_RUN 0x00000001
#define BP_SPDIF_CTRL_RUN 0
#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
#define BM_SPDIF_CTRL_CLKGATE 0x40000000
#define BM_SPDIF_CTRL_SFTRST 0x80000000
#define HW_SPDIF_STAT 0x10
#define HW_SPDIF_FRAMECTRL 0x20
#define HW_SPDIF_SRR 0x30
#define BM_SPDIF_SRR_RATE 0x000FFFFF
#define BP_SPDIF_SRR_RATE 0
#define BM_SPDIF_SRR_BASEMULT 0x70000000
#define BP_SPDIF_SRR_BASEMULT 28
#define HW_SPDIF_DEBUG 0x40
#define HW_SPDIF_DATA 0x50
#define HW_SPDIF_VERSION 0x60
arch/arm/mach-stmp378x/include/mach/regs-ssp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: SSP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
#define REGS_SSP1_PHYS 0x80010000
#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
#define REGS_SSP2_PHYS 0x80034000
#define REGS_SSP_SIZE 0x2000
#define HW_SSP_CTRL0 0x0
#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_SSP_CTRL0_XFER_COUNT 0
#define BM_SSP_CTRL0_ENABLE 0x00010000
#define BM_SSP_CTRL0_GET_RESP 0x00020000
#define BM_SSP_CTRL0_LONG_RESP 0x00080000
#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
#define BP_SSP_CTRL0_BUS_WIDTH 22
#define BM_SSP_CTRL0_DATA_XFER 0x01000000
#define BM_SSP_CTRL0_READ 0x02000000
#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
#define BM_SSP_CTRL0_LOCK_CS 0x08000000
#define BM_SSP_CTRL0_RUN 0x20000000
#define BM_SSP_CTRL0_CLKGATE 0x40000000
#define BM_SSP_CTRL0_SFTRST 0x80000000
#define HW_SSP_CMD0 0x10
#define BM_SSP_CMD0_CMD 0x000000FF
#define BP_SSP_CMD0_CMD 0
#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
#define BP_SSP_CMD0_BLOCK_COUNT 8
#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
#define BP_SSP_CMD0_BLOCK_SIZE 16
#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
#define BP_SSP_CMD1_CMD_ARG 0
#define HW_SSP_TIMING 0x50
#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
#define BP_SSP_TIMING_CLOCK_RATE 0
#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
#define BP_SSP_TIMING_TIMEOUT 16
#define HW_SSP_CTRL1 0x60
#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
#define BP_SSP_CTRL1_SSP_MODE 0
#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
#define BP_SSP_CTRL1_WORD_LENGTH 4
#define BM_SSP_CTRL1_POLARITY 0x00000200
#define BM_SSP_CTRL1_PHASE 0x00000400
#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
#define HW_SSP_DATA 0x70
#define HW_SSP_SDRESP0 0x80
#define HW_SSP_SDRESP1 0x90
#define HW_SSP_SDRESP2 0xA0
#define HW_SSP_SDRESP3 0xB0
#define HW_SSP_STATUS 0xC0
#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
#define BM_SSP_STATUS_TIMEOUT 0x00001000
#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
#define BM_SSP_STATUS_RESP_ERR 0x00008000
#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
#define BM_SSP_STATUS_CARD_DETECT 0x10000000
arch/arm/mach-stmp378x/include/mach/regs-sydma.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: SYDMA register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
#define REGS_SYDMA_PHYS 0x80026000
#define REGS_SYDMA_SIZE 0x2000
arch/arm/mach-stmp378x/include/mach/regs-timrot.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: TIMROT register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_TIMROT
#define _MACH_REGS_TIMROT
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
#define REGS_TIMROT_PHYS 0x80068000
#define REGS_TIMROT_SIZE 0x2000
#define HW_TIMROT_ROTCTRL 0x0
#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
#define BP_TIMROT_ROTCTRL_SELECT_A 0
#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
#define BP_TIMROT_ROTCTRL_SELECT_B 4
#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
#define BP_TIMROT_ROTCTRL_DIVIDER 16
#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
#define HW_TIMROT_ROTCOUNT 0x10
#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
#define BP_TIMROT_ROTCOUNT_UPDOWN 0
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
#define HW_TIMROT_TIMCTRLn 0x20
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
#define BP_TIMROT_TIMCTRLn_SELECT 0
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
#define HW_TIMROT_TIMCOUNTn 0x30
#endif
arch/arm/mach-stmp378x/include/mach/regs-tvenc.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: TVENC register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
#define REGS_TVENC_PHYS 0x80038000
#define REGS_TVENC_SIZE 0x2000
#define HW_TVENC_CTRL 0x0
#define BM_TVENC_CTRL_CLKGATE 0x40000000
#define BM_TVENC_CTRL_SFTRST 0x80000000
#define HW_TVENC_CONFIG 0x10
#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
#define BP_TVENC_CONFIG_ENCD_MODE 0
#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
#define BP_TVENC_CONFIG_SYNC_MODE 4
#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
#define BM_TVENC_CONFIG_CGAIN 0x0000C000
#define BP_TVENC_CONFIG_CGAIN 14
#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
#define BP_TVENC_CONFIG_YGAIN_SEL 16
#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
#define HW_TVENC_SYNCOFFSET 0x30
#define HW_TVENC_COLORSUB0 0xC0
#define HW_TVENC_COLORBURST 0x140
#define BM_TVENC_COLORBURST_PBA 0x00FF0000
#define BP_TVENC_COLORBURST_PBA 16
#define BM_TVENC_COLORBURST_NBA 0xFF000000
#define BP_TVENC_COLORBURST_NBA 24
#define HW_TVENC_MACROVISION0 0x150
#define HW_TVENC_MACROVISION1 0x160
#define HW_TVENC_MACROVISION2 0x170
#define HW_TVENC_MACROVISION3 0x180
#define HW_TVENC_MACROVISION4 0x190
#define HW_TVENC_DACCTRL 0x1A0
#define BM_TVENC_DACCTRL_RVAL 0x00000070
#define BP_TVENC_DACCTRL_RVAL 4
#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
#define BM_TVENC_DACCTRL_GAINUP 0x00040000
#define BM_TVENC_DACCTRL_GAINDN 0x00080000
arch/arm/mach-stmp378x/include/mach/regs-uartapp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: UARTAPP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
#define REGS_UARTAPP1_PHYS 0x8006C000
#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
#define REGS_UARTAPP2_PHYS 0x8006E000
#define REGS_UARTAPP_SIZE 0x2000
#define HW_UARTAPP_CTRL0 0x0
#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_UARTAPP_CTRL0_XFER_COUNT 0
#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
#define BM_UARTAPP_CTRL0_RUN 0x20000000
#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
#define BP_UARTAPP_CTRL1_XFER_COUNT 0
#define BM_UARTAPP_CTRL1_RUN 0x10000000
#define HW_UARTAPP_CTRL2 0x20
#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
#define BP_UARTAPP_CTRL2_UARTEN 0
#define BM_UARTAPP_CTRL2_TXE 0x00000100
#define BM_UARTAPP_CTRL2_RXE 0x00000200
#define BM_UARTAPP_CTRL2_RTS 0x00000800
#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
#define HW_UARTAPP_LINECTRL 0x30
#define BM_UARTAPP_LINECTRL_BRK 0x00000001
#define BP_UARTAPP_LINECTRL_BRK 0
#define BM_UARTAPP_LINECTRL_PEN 0x00000002
#define BM_UARTAPP_LINECTRL_EPS 0x00000004
#define BM_UARTAPP_LINECTRL_STP2 0x00000008
#define BM_UARTAPP_LINECTRL_FEN 0x00000010
#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
#define BP_UARTAPP_LINECTRL_WLEN 5
#define BM_UARTAPP_LINECTRL_SPS 0x00000080
#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
#define HW_UARTAPP_INTR 0x50
#define BM_UARTAPP_INTR_CTSMIS 0x00000002
#define BM_UARTAPP_INTR_RTIS 0x00000040
#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
#define BM_UARTAPP_INTR_RXIEN 0x00100000
#define BM_UARTAPP_INTR_RTIEN 0x00400000
#define HW_UARTAPP_DATA 0x60
#define HW_UARTAPP_STAT 0x70
#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
#define BP_UARTAPP_STAT_RXCOUNT 0
#define BM_UARTAPP_STAT_FERR 0x00010000
#define BM_UARTAPP_STAT_PERR 0x00020000
#define BM_UARTAPP_STAT_BERR 0x00040000
#define BM_UARTAPP_STAT_OERR 0x00080000
#define BM_UARTAPP_STAT_RXFE 0x01000000
#define BM_UARTAPP_STAT_TXFF 0x02000000
#define BM_UARTAPP_STAT_TXFE 0x08000000
#define BM_UARTAPP_STAT_CTS 0x10000000
#define HW_UARTAPP_VERSION 0x90
arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: UARTDBG register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
#define REGS_UARTDBG_PHYS 0x80070000
#define REGS_UARTDBG_SIZE 0x2000
#define HW_UARTDBGDR 0x00000000
#define BP_UARTDBGDR_UNAVAILABLE 16
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGDR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
#define BP_UARTDBGDR_RESERVED 12
#define BM_UARTDBGDR_RESERVED 0x0000F000
#define BF_UARTDBGDR_RESERVED(v) \
(((v) << 12) & BM_UARTDBGDR_RESERVED)
#define BM_UARTDBGDR_OE 0x00000800
#define BM_UARTDBGDR_BE 0x00000400
#define BM_UARTDBGDR_PE 0x00000200
#define BM_UARTDBGDR_FE 0x00000100
#define BP_UARTDBGDR_DATA 0
#define BM_UARTDBGDR_DATA 0x000000FF
#define BF_UARTDBGDR_DATA(v) \
(((v) << 0) & BM_UARTDBGDR_DATA)
#define HW_UARTDBGRSR_ECR 0x00000004
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
#define BP_UARTDBGRSR_ECR_EC 4
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
#define BF_UARTDBGRSR_ECR_EC(v) \
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
#define BM_UARTDBGRSR_ECR_OE 0x00000008
#define BM_UARTDBGRSR_ECR_BE 0x00000004
#define BM_UARTDBGRSR_ECR_PE 0x00000002
#define BM_UARTDBGRSR_ECR_FE 0x00000001
#define HW_UARTDBGFR 0x00000018
#define BP_UARTDBGFR_UNAVAILABLE 16
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGFR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
#define BP_UARTDBGFR_RESERVED 9
#define BM_UARTDBGFR_RESERVED 0x0000FE00
#define BF_UARTDBGFR_RESERVED(v) \
(((v) << 9) & BM_UARTDBGFR_RESERVED)
#define BM_UARTDBGFR_RI 0x00000100
#define BM_UARTDBGFR_TXFE 0x00000080
#define BM_UARTDBGFR_RXFF 0x00000040
#define BM_UARTDBGFR_TXFF 0x00000020
#define BM_UARTDBGFR_RXFE 0x00000010
#define BM_UARTDBGFR_BUSY 0x00000008
#define BM_UARTDBGFR_DCD 0x00000004
#define BM_UARTDBGFR_DSR 0x00000002
#define BM_UARTDBGFR_CTS 0x00000001
#define HW_UARTDBGILPR 0x00000020
#define BP_UARTDBGILPR_UNAVAILABLE 8
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
#define BP_UARTDBGILPR_ILPDVSR 0
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
#define BF_UARTDBGILPR_ILPDVSR(v) \
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
#define HW_UARTDBGIBRD 0x00000024
#define BP_UARTDBGIBRD_UNAVAILABLE 16
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
#define HW_UARTDBGFBRD 0x00000028
#define BP_UARTDBGFBRD_UNAVAILABLE 8
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
#define BP_UARTDBGFBRD_RESERVED 6
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
#define BF_UARTDBGFBRD_RESERVED(v) \
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
#define HW_UARTDBGLCR_H 0x0000002c
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
#define BP_UARTDBGLCR_H_RESERVED 8
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
#define BF_UARTDBGLCR_H_RESERVED(v) \
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
#define BM_UARTDBGLCR_H_SPS 0x00000080
#define BP_UARTDBGLCR_H_WLEN 5
#define BM_UARTDBGLCR_H_WLEN 0x00000060
#define BF_UARTDBGLCR_H_WLEN(v) \
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
#define BM_UARTDBGLCR_H_FEN 0x00000010
#define BM_UARTDBGLCR_H_STP2 0x00000008
#define BM_UARTDBGLCR_H_EPS 0x00000004
#define BM_UARTDBGLCR_H_PEN 0x00000002
#define BM_UARTDBGLCR_H_BRK 0x00000001
#define HW_UARTDBGCR 0x00000030
#define BP_UARTDBGCR_UNAVAILABLE 16
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGCR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
#define BM_UARTDBGCR_CTSEN 0x00008000
#define BM_UARTDBGCR_RTSEN 0x00004000
#define BM_UARTDBGCR_OUT2 0x00002000
#define BM_UARTDBGCR_OUT1 0x00001000
#define BM_UARTDBGCR_RTS 0x00000800
#define BM_UARTDBGCR_DTR 0x00000400
#define BM_UARTDBGCR_RXE 0x00000200
#define BM_UARTDBGCR_TXE 0x00000100
#define BM_UARTDBGCR_LBE 0x00000080
#define BP_UARTDBGCR_RESERVED 3
#define BM_UARTDBGCR_RESERVED 0x00000078
#define BF_UARTDBGCR_RESERVED(v) \
(((v) << 3) & BM_UARTDBGCR_RESERVED)
#define BM_UARTDBGCR_SIRLP 0x00000004
#define BM_UARTDBGCR_SIREN 0x00000002
#define BM_UARTDBGCR_UARTEN 0x00000001
#define HW_UARTDBGIFLS 0x00000034
#define BP_UARTDBGIFLS_UNAVAILABLE 16
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
#define BP_UARTDBGIFLS_RESERVED 6
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
#define BF_UARTDBGIFLS_RESERVED(v) \
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
#define BP_UARTDBGIFLS_RXIFLSEL 3
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
#define BP_UARTDBGIFLS_TXIFLSEL 0
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
#define HW_UARTDBGIMSC 0x00000038
#define BP_UARTDBGIMSC_UNAVAILABLE 16
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
#define BP_UARTDBGIMSC_RESERVED 11
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
#define BF_UARTDBGIMSC_RESERVED(v) \
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
#define BM_UARTDBGIMSC_OEIM 0x00000400
#define BM_UARTDBGIMSC_BEIM 0x00000200
#define BM_UARTDBGIMSC_PEIM 0x00000100
#define BM_UARTDBGIMSC_FEIM 0x00000080
#define BM_UARTDBGIMSC_RTIM 0x00000040
#define BM_UARTDBGIMSC_TXIM 0x00000020
#define BM_UARTDBGIMSC_RXIM 0x00000010
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
#define BM_UARTDBGIMSC_RIMIM 0x00000001
#define HW_UARTDBGRIS 0x0000003c
#define BP_UARTDBGRIS_UNAVAILABLE 16
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
#define BP_UARTDBGRIS_RESERVED 11
#define BM_UARTDBGRIS_RESERVED 0x0000F800
#define BF_UARTDBGRIS_RESERVED(v) \
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
#define BM_UARTDBGRIS_OERIS 0x00000400
#define BM_UARTDBGRIS_BERIS 0x00000200
#define BM_UARTDBGRIS_PERIS 0x00000100
#define BM_UARTDBGRIS_FERIS 0x00000080
#define BM_UARTDBGRIS_RTRIS 0x00000040
#define BM_UARTDBGRIS_TXRIS 0x00000020
#define BM_UARTDBGRIS_RXRIS 0x00000010
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
#define BM_UARTDBGRIS_RIRMIS 0x00000001
#define HW_UARTDBGMIS 0x00000040
#define BP_UARTDBGMIS_UNAVAILABLE 16
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
#define BP_UARTDBGMIS_RESERVED 11
#define BM_UARTDBGMIS_RESERVED 0x0000F800
#define BF_UARTDBGMIS_RESERVED(v) \
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
#define BM_UARTDBGMIS_OEMIS 0x00000400
#define BM_UARTDBGMIS_BEMIS 0x00000200
#define BM_UARTDBGMIS_PEMIS 0x00000100
#define BM_UARTDBGMIS_FEMIS 0x00000080
#define BM_UARTDBGMIS_RTMIS 0x00000040
#define BM_UARTDBGMIS_TXMIS 0x00000020
#define BM_UARTDBGMIS_RXMIS 0x00000010
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
#define BM_UARTDBGMIS_RIMMIS 0x00000001
#define HW_UARTDBGICR 0x00000044
#define BP_UARTDBGICR_UNAVAILABLE 16
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGICR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
#define BP_UARTDBGICR_RESERVED 11
#define BM_UARTDBGICR_RESERVED 0x0000F800
#define BF_UARTDBGICR_RESERVED(v) \
(((v) << 11) & BM_UARTDBGICR_RESERVED)
#define BM_UARTDBGICR_OEIC 0x00000400
#define BM_UARTDBGICR_BEIC 0x00000200
#define BM_UARTDBGICR_PEIC 0x00000100
#define BM_UARTDBGICR_FEIC 0x00000080
#define BM_UARTDBGICR_RTIC 0x00000040
#define BM_UARTDBGICR_TXIC 0x00000020
#define BM_UARTDBGICR_RXIC 0x00000010
#define BM_UARTDBGICR_DSRMIC 0x00000008
#define BM_UARTDBGICR_DCDMIC 0x00000004
#define BM_UARTDBGICR_CTSMIC 0x00000002
#define BM_UARTDBGICR_RIMIC 0x00000001
#define HW_UARTDBGDMACR 0x00000048
#define BP_UARTDBGDMACR_UNAVAILABLE 16
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
#define BP_UARTDBGDMACR_RESERVED 3
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
#define BF_UARTDBGDMACR_RESERVED(v) \
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: USBCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
#define REGS_USBCTRL_PHYS 0x80080000
#define REGS_USBCTRL_SIZE 0x2000
#define HW_USBCTRL_USBCMD 0x140
#define BM_USBCTRL_USBCMD_RS 0x00000001
#define BP_USBCTRL_USBCMD_RS 0
#define BM_USBCTRL_USBCMD_RST 0x00000002
#define HW_USBCTRL_USBINTR 0x148
#define BM_USBCTRL_USBINTR_UE 0x00000001
#define BP_USBCTRL_USBINTR_UE 0
#define HW_USBCTRL_PORTSC1 0x184
#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
#define HW_USBCTRL_OTGSC 0x1A4
#define BM_USBCTRL_OTGSC_ID 0x00000100
#define BM_USBCTRL_OTGSC_IDIS 0x00010000
#define BM_USBCTRL_OTGSC_IDIE 0x01000000
arch/arm/mach-stmp378x/include/mach/regs-usbphy.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: USBPHY register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
#define REGS_USBPHY_PHYS 0x8007C000
#define REGS_USBPHY_SIZE 0x2000
#define HW_USBPHY_PWD 0x0
#define HW_USBPHY_CTRL 0x30
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
#define BM_USBPHY_CTRL_CLKGATE 0x40000000
#define BM_USBPHY_CTRL_SFTRST 0x80000000
#define HW_USBPHY_STATUS 0x40
#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
arch/arm/mach-stmp378x/stmp378x.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP378X platform support
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <asm/dma.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/pins.h>
#include <mach/pinmux.h>
#include <mach/dma.h>
#include <mach/hardware.h>
#include <mach/system.h>
#include <mach/platform.h>
#include <mach/stmp3xxx.h>
#include <mach/regs-icoll.h>
#include <mach/regs-apbh.h>
#include <mach/regs-apbx.h>
#include <mach/regs-pxp.h>
#include <mach/regs-i2c.h>
#include "stmp378x.h"
/*
* IRQ handling
*/
static void stmp378x_ack_irq(struct irq_data *d)
{
/* Tell ICOLL to release IRQ line */
__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
/* ACK current interrupt */
__raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
/* Barrier */
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}
static void stmp378x_mask_irq(struct irq_data *d)
{
/* IRQ disable */
stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
}
static void stmp378x_unmask_irq(struct irq_data *d)
{
/* IRQ enable */
stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
}
static struct irq_chip stmp378x_chip = {
.irq_ack = stmp378x_ack_irq,
.irq_mask = stmp378x_mask_irq,
.irq_unmask = stmp378x_unmask_irq,
};
void __init stmp378x_init_irq(void)
{
stmp3xxx_init_irq(&stmp378x_chip);
}
/*
* DMA interrupt handling
*/
void stmp3xxx_arch_dma_enable_interrupt(int channel)
{
void __iomem *c1, *c2;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
break;
case STMP3XXX_BUS_APBX:
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
break;
default:
return;
}
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
void stmp3xxx_arch_dma_clear_interrupt(int channel)
{
void __iomem *c1, *c2;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
break;
case STMP3XXX_BUS_APBX:
c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
break;
default:
return;
}
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
int stmp3xxx_arch_dma_is_interrupt(int channel)
{
int r = 0;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
case STMP3XXX_BUS_APBX:
r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
}
return r;
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
void stmp3xxx_arch_dma_reset_channel(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
void __iomem *c0;
u32 mask;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
break;
case STMP3XXX_BUS_APBX:
c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
break;
default:
return;
}
/* Reset channel and wait for it to complete */
stmp3xxx_setl(mask, c0);
while (__raw_readl(c0) & mask)
cpu_relax();
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
void stmp3xxx_arch_dma_freeze(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
u32 mask = 1 << chbit;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
void stmp3xxx_arch_dma_unfreeze(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
u32 mask = 1 << chbit;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
/*
* The registers are all very closely mapped, so we might as well map them all
* with a single mapping
*
* Logical Physical
* f0000000 80000000 On-chip registers
* f1000000 00000000 32k on-chip SRAM
*/
static struct map_desc stmp378x_io_desc[] __initdata = {
{
.virtual = (u32)STMP3XXX_REGS_BASE,
.pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
.length = STMP3XXX_REGS_SIZE,
.type = MT_DEVICE,
},
{
.virtual = (u32)STMP3XXX_OCRAM_BASE,
.pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
.length = STMP3XXX_OCRAM_SIZE,
.type = MT_DEVICE,
},
};
static u64 common_dmamask = DMA_BIT_MASK(32);
/*
* devices that are present only on stmp378x, not on all 3xxx boards:
* PxP
* I2C
*/
static struct resource pxp_resource[] = {
{
.flags = IORESOURCE_MEM,
.start = REGS_PXP_PHYS,
.end = REGS_PXP_PHYS + REGS_PXP_SIZE,
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_PXP,
.end = IRQ_PXP,
},
};
struct platform_device stmp378x_pxp = {
.name = "stmp3xxx-pxp",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(pxp_resource),
.resource = pxp_resource,
};
static struct resource i2c_resources[] = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_I2C_ERROR,
.end = IRQ_I2C_ERROR,
}, {
.flags = IORESOURCE_MEM,
.start = REGS_I2C_PHYS,
.end = REGS_I2C_PHYS + REGS_I2C_SIZE,
}, {
.flags = IORESOURCE_DMA,
.start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
.end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
},
};
struct platform_device stmp378x_i2c = {
.name = "i2c_stmp3xxx",
.id = 0,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = i2c_resources,
.num_resources = ARRAY_SIZE(i2c_resources),
};
void __init stmp378x_map_io(void)
{
iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
}
arch/arm/mach-stmp378x/stmp378x.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X internal functions and data declarations
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_STMP378X_H
#define __MACH_STMP378X_H
void stmp378x_map_io(void);
void stmp378x_init_irq(void);
extern struct platform_device stmp378x_pxp, stmp378x_i2c;
#endif /* __MACH_STMP378X_COMMON_H */
arch/arm/mach-stmp378x/stmp378x_devb.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP378X development board support
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/pins.h>
#include <mach/pinmux.h>
#include <mach/platform.h>
#include <mach/stmp3xxx.h>
#include <mach/mmc.h>
#include <mach/gpmi.h>
#include "stmp378x.h"
static struct platform_device *devices[] = {
&stmp3xxx_dbguart,
&stmp3xxx_appuart,
&stmp3xxx_watchdog,
&stmp3xxx_touchscreen,
&stmp3xxx_rtc,
&stmp3xxx_keyboard,
&stmp3xxx_framebuffer,
&stmp3xxx_backlight,
&stmp3xxx_rotdec,
&stmp3xxx_persistent,
&stmp3xxx_dcp_bootstream,
&stmp3xxx_dcp,
&stmp3xxx_battery,
&stmp378x_pxp,
&stmp378x_i2c,
};
static struct pin_desc i2c_pins_desc[] = {
{ PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
};
static struct pin_group i2c_pins = {
.pins = i2c_pins_desc,
.nr_pins = ARRAY_SIZE(i2c_pins_desc),
};
static struct pin_desc dbguart_pins_0[] = {
{ PINID_PWM0, PIN_FUN3, },
{ PINID_PWM1, PIN_FUN3, },
};
static struct pin_group dbguart_pins[] = {
[0] = {
.pins = dbguart_pins_0,
.nr_pins = ARRAY_SIZE(dbguart_pins_0),
},
};
static int dbguart_pins_control(int id, int request)
{
int r = 0;
if (request)
r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
else
stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
return r;
}
static struct pin_desc appuart_pins_0[] = {
{ PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
};
static struct pin_desc appuart_pins_1[] = {
#if 0 /* enable these when second appuart will be connected */
{ PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
#endif
};
static struct pin_desc mmc_pins_desc[] = {
{ PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
{ PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
{ PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
{ PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
{ PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
{ PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
{ PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
};
static struct pin_group mmc_pins = {
.pins = mmc_pins_desc,
.nr_pins = ARRAY_SIZE(mmc_pins_desc),
};
static int stmp3xxxmmc_get_wp(void)
{
return gpio_get_value(PINID_PWM4);
}
static int stmp3xxxmmc_hw_init_ssp1(void)
{
int ret;
ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
if (ret)
goto out;
/* Configure write protect GPIO pin */
ret = gpio_request(PINID_PWM4, "mmc wp");
if (ret)
goto out_wp;
gpio_direction_input(PINID_PWM4);
/* Configure POWER pin as gpio to drive power to MMC slot */
ret = gpio_request(PINID_PWM3, "mmc power");
if (ret)
goto out_power;
gpio_direction_output(PINID_PWM3, 0);
mdelay(100);
return 0;
out_power:
gpio_free(PINID_PWM4);
out_wp:
stmp3xxx_release_pin_group(&mmc_pins, "mmc");
out:
return ret;
}
static void stmp3xxxmmc_hw_release_ssp1(void)
{
gpio_free(PINID_PWM3);
gpio_free(PINID_PWM4);
stmp3xxx_release_pin_group(&mmc_pins, "mmc");
}
static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
{
stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
}
static unsigned long
stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
{
struct clk *ssp, *parent;
char *p;
long r;
ssp = clk_get(NULL, "ssp");
/* using SSP1, no timeout, clock rate 1 */
writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
BF(0xFFFF, SSP_TIMING_TIMEOUT),
base + HW_SSP_TIMING);
p = (hz > 1000000) ? "io" : "osc_24M";
parent = clk_get(NULL, p);
clk_set_parent(ssp, parent);
r = clk_set_rate(ssp, 2 * hz / 1000);
clk_put(parent);
clk_put(ssp);
return hz;
}
static struct stmp3xxxmmc_platform_data mmc_data = {
.hw_init = stmp3xxxmmc_hw_init_ssp1,
.hw_release = stmp3xxxmmc_hw_release_ssp1,
.get_wp = stmp3xxxmmc_get_wp,
.cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
.setclock = stmp3xxxmmc_setclock_ssp1,
};
static struct pin_group appuart_pins[] = {
[0] = {
.pins = appuart_pins_0,
.nr_pins = ARRAY_SIZE(appuart_pins_0),
},
[1] = {
.pins = appuart_pins_1,
.nr_pins = ARRAY_SIZE(appuart_pins_1),
},
};
static struct pin_desc ssp1_pins_desc[] = {
{ PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
{ PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
{ PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
{ PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
};
static struct pin_desc ssp2_pins_desc[] = {
{ PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
{ PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
{ PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
{ PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
};
static struct pin_group ssp1_pins = {
.pins = ssp1_pins_desc,
.nr_pins = ARRAY_SIZE(ssp1_pins_desc),
};
static struct pin_group ssp2_pins = {
.pins = ssp1_pins_desc,
.nr_pins = ARRAY_SIZE(ssp2_pins_desc),
};
static struct pin_desc gpmi_pins_desc[] = {
{ PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
{ PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
{ PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
{ PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
};
static struct pin_group gpmi_pins = {
.pins = gpmi_pins_desc,
.nr_pins = ARRAY_SIZE(gpmi_pins_desc),
};
static struct mtd_partition gpmi_partitions[] = {
[0] = {
.name = "boot",
.size = 10 * SZ_1M,
.offset = 0,
},
[1] = {
.name = "data",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
},
};
static struct gpmi_platform_data gpmi_data = {
.pins = &gpmi_pins,
.nr_parts = ARRAY_SIZE(gpmi_partitions),
.parts = gpmi_partitions,
.part_types = { "cmdline", NULL },
};
static struct spi_board_info spi_board_info[] __initdata = {
#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
{
.modalias = "enc28j60",
.max_speed_hz = 6 * 1000 * 1000,
.bus_num = 1,
.chip_select = 0,
.platform_data = NULL,
},
#endif
};
static void __init stmp378x_devb_init(void)
{
stmp3xxx_pinmux_init(NR_REAL_IRQS);
/* init stmp3xxx platform */
stmp3xxx_init();
stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
stmp3xxx_appuart.dev.platform_data = appuart_pins;
stmp3xxx_mmc.dev.platform_data = &mmc_data;
stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
stmp378x_i2c.dev.platform_data = &i2c_pins;
/* register spi devices */
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
/* add board's devices */
platform_add_devices(devices, ARRAY_SIZE(devices));
/* add devices selected by command line ssp1= and ssp2= options */
stmp3xxx_ssp1_device_register();
stmp3xxx_ssp2_device_register();
}
MACHINE_START(STMP378X, "STMP378X")
.boot_params = 0x40000100,
.map_io = stmp378x_map_io,
.init_irq = stmp378x_init_irq,
.timer = &stmp3xxx_timer,
.init_machine = stmp378x_devb_init,
MACHINE_END
arch/arm/mach-stmp37xx/Makefile deleted 100644 → 0
View file @ e8765afe
obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
arch/arm/mach-stmp37xx/Makefile.boot deleted 100644 → 0
View file @ e8765afe
zreladdr-y := 0x40008000
params_phys-y := 0x40000100
initrd_phys-y := 0x40800000
arch/arm/mach-stmp37xx/include/mach/entry-macro.S deleted 100644 → 0
View file @ e8765afe
/*
* Low-level IRQ helper macros for Freescale STMP37XX
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \base, #0xf0000000 @ vm address of IRQ controller
ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
cmp \irqnr, #0x3f
movne \irqstat, #0 @ Ack this IRQ
strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
moveqs \irqnr, #0 @ Zero flag set for no IRQ
.endm
.macro get_irqnr_preamble, base, tmp
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
arch/arm/mach-stmp37xx/include/mach/irqs.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX interrupts
*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef _ASM_ARCH_IRQS_H
#define _ASM_ARCH_IRQS_H
#define IRQ_DEBUG_UART 0
#define IRQ_COMMS_RX 1
#define IRQ_COMMS_TX 1
#define IRQ_SSP2_ERROR 2
#define IRQ_VDD5V 3
#define IRQ_HEADPHONE_SHORT 4
#define IRQ_DAC_DMA 5
#define IRQ_DAC_ERROR 6
#define IRQ_ADC_DMA 7
#define IRQ_ADC_ERROR 8
#define IRQ_SPDIF_DMA 9
#define IRQ_SAIF2_DMA 9
#define IRQ_SPDIF_ERROR 10
#define IRQ_SAIF1_IRQ 10
#define IRQ_SAIF2_IRQ 10
#define IRQ_USB_CTRL 11
#define IRQ_USB_WAKEUP 12
#define IRQ_GPMI_DMA 13
#define IRQ_SSP1_DMA 14
#define IRQ_SSP_ERROR 15
#define IRQ_GPIO0 16
#define IRQ_GPIO1 17
#define IRQ_GPIO2 18
#define IRQ_SAIF1_DMA 19
#define IRQ_SSP2_DMA 20
#define IRQ_ECC8_IRQ 21
#define IRQ_RTC_ALARM 22
#define IRQ_UARTAPP_TX_DMA 23
#define IRQ_UARTAPP_INTERNAL 24
#define IRQ_UARTAPP_RX_DMA 25
#define IRQ_I2C_DMA 26
#define IRQ_I2C_ERROR 27
#define IRQ_TIMER0 28
#define IRQ_TIMER1 29
#define IRQ_TIMER2 30
#define IRQ_TIMER3 31
#define IRQ_BATT_BRNOUT 32
#define IRQ_VDDD_BRNOUT 33
#define IRQ_VDDIO_BRNOUT 34
#define IRQ_VDD18_BRNOUT 35
#define IRQ_TOUCH_DETECT 36
#define IRQ_LRADC_CH0 37
#define IRQ_LRADC_CH1 38
#define IRQ_LRADC_CH2 39
#define IRQ_LRADC_CH3 40
#define IRQ_LRADC_CH4 41
#define IRQ_LRADC_CH5 42
#define IRQ_LRADC_CH6 43
#define IRQ_LRADC_CH7 44
#define IRQ_LCDIF_DMA 45
#define IRQ_LCDIF_ERROR 46
#define IRQ_DIGCTL_DEBUG_TRAP 47
#define IRQ_RTC_1MSEC 48
#define IRQ_DRI_DMA 49
#define IRQ_DRI_ATTENTION 50
#define IRQ_GPMI_ATTENTION 51
#define IRQ_IR 52
#define IRQ_DCP_VMI 53
#define IRQ_DCP 54
#define IRQ_RESERVED_55 55
#define IRQ_RESERVED_56 56
#define IRQ_RESERVED_57 57
#define IRQ_RESERVED_58 58
#define IRQ_RESERVED_59 59
#define SW_IRQ_60 60
#define SW_IRQ_61 61
#define SW_IRQ_62 62
#define SW_IRQ_63 63
#define NR_REAL_IRQS 64
#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
/* TIMER and BRNOUT are FIQ capable */
#define FIQ_START IRQ_TIMER0
/* Hard disk IRQ is a GPMI attention IRQ */
#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
#endif /* _ASM_ARCH_IRQS_H */
arch/arm/mach-stmp37xx/include/mach/pins.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX SoC pin multiplexing
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_PINS_H
#define __ASM_ARCH_PINS_H
/*
* Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
* interface this pin belongs to.
*/
/* Bank 0 */
#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
/* Bank 1 */
#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
/* Bank 2 */
#define PINID_PWM0 STMP3XXX_PINID(2, 0)
#define PINID_PWM1 STMP3XXX_PINID(2, 1)
#define PINID_PWM2 STMP3XXX_PINID(2, 2)
#define PINID_PWM3 STMP3XXX_PINID(2, 3)
#define PINID_PWM4 STMP3XXX_PINID(2, 4)
#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
/* Bank 3 */
#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
#endif /* __ASM_ARCH_PINS_H */
arch/arm/mach-stmp37xx/include/mach/regs-apbh.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: APBH register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_APBH
#define _MACH_REGS_APBH
#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
#define HW_APBH_CTRL0 0x0
#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
#define BP_APBH_CTRL0_RESET_CHANNEL 16
#define BM_APBH_CTRL0_CLKGATE 0x40000000
#define BM_APBH_CTRL0_SFTRST 0x80000000
#define HW_APBH_CTRL1 0x10
#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
#define HW_APBH_DEVSEL 0x20
#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
#define HW_APBH_CHn_NXTCMDAR 0x50
#define BM_APBH_CHn_CMD_MODE 0x00000003
#define BP_APBH_CHn_CMD_MODE 0x00000001
#define BV_APBH_CHn_CMD_MODE_NOOP 0
#define BV_APBH_CHn_CMD_MODE_WRITE 1
#define BV_APBH_CHn_CMD_MODE_READ 2
#define BV_APBH_CHn_CMD_MODE_SENSE 3
#define BM_APBH_CHn_CMD_CHAIN 0x00000004
#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBH_CHn_CMD_CMDWORDS 12
#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBH_CHn_CMD_XFER_COUNT 16
#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
#define HW_APBH_CHn_SEMA 0x80
#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBH_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp37xx/include/mach/regs-apbx.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: APBX register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_APBX
#define _MACH_REGS_APBX
#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
#define HW_APBX_CTRL0 0x0
#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
#define BP_APBX_CTRL0_RESET_CHANNEL 16
#define BM_APBX_CTRL0_CLKGATE 0x40000000
#define BM_APBX_CTRL0_SFTRST 0x80000000
#define HW_APBX_CTRL1 0x10
#define HW_APBX_DEVSEL 0x20
#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
#define HW_APBX_CHn_NXTCMDAR 0x50
#define BM_APBX_CHn_CMD_MODE 0x00000003
#define BP_APBX_CHn_CMD_MODE 0x00000001
#define BV_APBX_CHn_CMD_MODE_NOOP 0
#define BV_APBX_CHn_CMD_MODE_WRITE 1
#define BV_APBX_CHn_CMD_MODE_READ 2
#define BV_APBX_CHn_CMD_MODE_SENSE 3
#define BM_APBX_CHn_CMD_COMMAND 0x00000003
#define BP_APBX_CHn_CMD_COMMAND 0
#define BM_APBX_CHn_CMD_CHAIN 0x00000004
#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
#define BP_APBX_CHn_CMD_CMDWORDS 12
#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
#define BP_APBX_CHn_CMD_XFER_COUNT 16
#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
#define HW_APBX_CHn_BAR 0x70
#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
#define HW_APBX_CHn_SEMA 0x80
#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
#define BP_APBX_CHn_SEMA_PHORE 16
#endif
arch/arm/mach-stmp37xx/include/mach/regs-audioin.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: AUDIOIN register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
#define HW_AUDIOIN_CTRL 0x0
#define BM_AUDIOIN_CTRL_RUN 0x00000001
#define BP_AUDIOIN_CTRL_RUN 0
#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
#define HW_AUDIOIN_STAT 0x10
#define HW_AUDIOIN_ADCSRR 0x20
#define HW_AUDIOIN_ADCVOLUME 0x30
#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
#define HW_AUDIOIN_ADCDEBUG 0x40
#define HW_AUDIOIN_ADCVOL 0x50
#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
#define HW_AUDIOIN_MICLINE 0x60
#define HW_AUDIOIN_ANACLKCTRL 0x70
#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
#define HW_AUDIOIN_DATA 0x80
arch/arm/mach-stmp37xx/include/mach/regs-audioout.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: AUDIOOUT register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
#define HW_AUDIOOUT_CTRL 0x0
#define BM_AUDIOOUT_CTRL_RUN 0x00000001
#define BP_AUDIOOUT_CTRL_RUN 0
#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
#define HW_AUDIOOUT_STAT 0x10
#define HW_AUDIOOUT_DACSRR 0x20
#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
#define BP_AUDIOOUT_DACSRR_SRC_INT 16
#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
#define BP_AUDIOOUT_DACSRR_BASEMULT 28
#define HW_AUDIOOUT_DACVOLUME 0x30
#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
#define HW_AUDIOOUT_DACDEBUG 0x40
#define HW_AUDIOOUT_HPVOL 0x50
#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
#define HW_AUDIOOUT_PWRDN 0x70
#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
#define HW_AUDIOOUT_REFCTRL 0x80
#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
#define HW_AUDIOOUT_ANACTRL 0x90
#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
#define HW_AUDIOOUT_TEST 0xA0
#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
#define HW_AUDIOOUT_BISTCTRL 0xB0
#define HW_AUDIOOUT_BISTSTAT0 0xC0
#define HW_AUDIOOUT_BISTSTAT1 0xD0
#define HW_AUDIOOUT_ANACLKCTRL 0xE0
#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
#define HW_AUDIOOUT_DATA 0xF0
#define HW_AUDIOOUT_LINEOUTCTRL 0x100
#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
#define HW_AUDIOOUT_VERSION 0x200
arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: CLKCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_CLKCTRL
#define _MACH_REGS_CLKCTRL
#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
#define HW_CLKCTRL_PLLCTRL0 0x0
#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
#define HW_CLKCTRL_CPU 0x20
#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
#define BP_CLKCTRL_CPU_DIV_CPU 0
#define HW_CLKCTRL_HBUS 0x30
#define BM_CLKCTRL_HBUS_DIV 0x0000001F
#define BP_CLKCTRL_HBUS_DIV 0
#define HW_CLKCTRL_XBUS 0x40
#define HW_CLKCTRL_XTAL 0x50
#define HW_CLKCTRL_PIX 0x60
#define BM_CLKCTRL_PIX_DIV 0x00007FFF
#define BP_CLKCTRL_PIX_DIV 0
#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
#define HW_CLKCTRL_SSP 0x70
#define HW_CLKCTRL_GPMI 0x80
#define HW_CLKCTRL_SPDIF 0x90
#define HW_CLKCTRL_EMI 0xA0
#define HW_CLKCTRL_IR 0xB0
#define HW_CLKCTRL_SAIF 0xC0
#define HW_CLKCTRL_FRAC 0xD0
#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
#define BP_CLKCTRL_FRAC_EMIFRAC 8
#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
#define BP_CLKCTRL_FRAC_PIXFRAC 16
#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
#define HW_CLKCTRL_CLKSEQ 0xE0
#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
#define HW_CLKCTRL_RESET 0xF0
#define BM_CLKCTRL_RESET_DIG 0x00000001
#define BP_CLKCTRL_RESET_DIG 0
#endif
arch/arm/mach-stmp37xx/include/mach/regs-digctl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: DIGCTL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
#define HW_DIGCTL_CTRL 0x0
#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: ECC8 register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
#define HW_ECC8_CTRL 0x0
#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
#define BP_ECC8_CTRL_COMPLETE_IRQ 0
#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
#define HW_ECC8_STATUS0 0x10
#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
#define BM_ECC8_STATUS0_CORRECTED 0x00000008
#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
#define BP_ECC8_STATUS0_STATUS_AUX 8
#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
#define BP_ECC8_STATUS0_COMPLETED_CE 16
#define HW_ECC8_STATUS1 0x20
arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: GPMI register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
#define REGS_GPMI_PHYS 0x8000C000
#define REGS_GPMI_SIZE 0x2000
#define HW_GPMI_CTRL0 0x0
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_GPMI_CTRL0_XFER_COUNT 0
#define BM_GPMI_CTRL0_CS 0x00300000
#define BP_GPMI_CTRL0_CS 20
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
#define BP_GPMI_CTRL0_COMMAND_MODE 24
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
#define BM_GPMI_CTRL0_RUN 0x20000000
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
#define BM_GPMI_CTRL0_SFTRST 0x80000000
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
#define BP_GPMI_ECCCTRL_ECC_CMD 13
#define HW_GPMI_CTRL1 0x60
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
#define BP_GPMI_CTRL1_GPMI_MODE 0
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
#define HW_GPMI_TIMING0 0x70
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
#define BP_GPMI_TIMING0_DATA_SETUP 0
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
#define BP_GPMI_TIMING0_DATA_HOLD 8
#define HW_GPMI_TIMING1 0x80
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
arch/arm/mach-stmp37xx/include/mach/regs-i2c.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: I2C register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
#define REGS_I2C_PHYS 0x80058000
#define REGS_I2C_SIZE 0x2000
#define HW_I2C_CTRL0 0x0
#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_I2C_CTRL0_XFER_COUNT 0
#define BM_I2C_CTRL0_DIRECTION 0x00010000
#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
#define BM_I2C_CTRL0_CLKGATE 0x40000000
#define BM_I2C_CTRL0_SFTRST 0x80000000
#define HW_I2C_TIMING0 0x10
#define HW_I2C_TIMING1 0x20
#define HW_I2C_TIMING2 0x30
#define HW_I2C_CTRL1 0x40
#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
#define BP_I2C_CTRL1_SLAVE_IRQ 0
#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
#define HW_I2C_VERSION 0x90
arch/arm/mach-stmp37xx/include/mach/regs-icoll.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: ICOLL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_ICOLL
#define _MACH_REGS_ICOLL
#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
#define HW_ICOLL_VECTOR 0x0
#define HW_ICOLL_LEVELACK 0x10
#define HW_ICOLL_CTRL 0x20
#define BM_ICOLL_CTRL_CLKGATE 0x40000000
#define BM_ICOLL_CTRL_SFTRST 0x80000000
#define HW_ICOLL_STAT 0x30
#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
#define HW_ICOLL_PRIORITYn 0x60
#endif
arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: LCDIF register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
#define REGS_LCDIF_PHYS 0x80030000
#define REGS_LCDIF_SIZE 0x2000
#define HW_LCDIF_CTRL 0x0
#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
#define BP_LCDIF_CTRL_COUNT 0
#define BM_LCDIF_CTRL_RUN 0x00010000
#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
#define BM_LCDIF_CTRL_CLKGATE 0x40000000
#define BM_LCDIF_CTRL_SFTRST 0x80000000
#define HW_LCDIF_CTRL1 0x10
#define BM_LCDIF_CTRL1_RESET 0x00000001
#define BP_LCDIF_CTRL1_RESET 0
#define BM_LCDIF_CTRL1_MODE86 0x00000002
#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
#define HW_LCDIF_TIMING 0x20
#define HW_LCDIF_VDCTRL0 0x30
#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
#define HW_LCDIF_VDCTRL1 0x40
#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
#define HW_LCDIF_VDCTRL2 0x50
#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
#define HW_LCDIF_VDCTRL3 0x60
#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
arch/arm/mach-stmp37xx/include/mach/regs-lradc.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: LRADC register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
#define HW_LRADC_CTRL0 0x0
#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
#define BP_LRADC_CTRL0_SCHEDULE 0
#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
#define BM_LRADC_CTRL0_CLKGATE 0x40000000
#define BM_LRADC_CTRL0_SFTRST 0x80000000
#define HW_LRADC_CTRL1 0x10
#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
#define BP_LRADC_CTRL1_LRADC0_IRQ 0
#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
#define HW_LRADC_CTRL2 0x20
#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
#define HW_LRADC_CTRL3 0x30
#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
#define BP_LRADC_CTRL3_CYCLE_TIME 8
#define HW_LRADC_STATUS 0x40
#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
#define HW_LRADC_CHn 0x50
#define BM_LRADC_CHn_VALUE 0x0003FFFF
#define BP_LRADC_CHn_VALUE 0
#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
#define BP_LRADC_CHn_NUM_SAMPLES 24
#define BM_LRADC_CHn_ACCUMULATE 0x20000000
#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
#define HW_LRADC_DELAYn 0xD0
#define BM_LRADC_DELAYn_DELAY 0x000007FF
#define BP_LRADC_DELAYn_DELAY 0
#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
#define BP_LRADC_DELAYn_LOOP_COUNT 11
#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
#define BM_LRADC_DELAYn_KICK 0x00100000
#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
#define HW_LRADC_CTRL4 0x140
#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
#define BP_LRADC_CTRL4_LRADC6SELECT 24
#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
#define BP_LRADC_CTRL4_LRADC7SELECT 28
arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: PINCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_PINCTRL
#define _MACH_REGS_PINCTRL
#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
#define HW_PINCTRL_MUXSEL0 0x100
#define HW_PINCTRL_MUXSEL1 0x110
#define HW_PINCTRL_MUXSEL2 0x120
#define HW_PINCTRL_MUXSEL3 0x130
#define HW_PINCTRL_MUXSEL4 0x140
#define HW_PINCTRL_MUXSEL5 0x150
#define HW_PINCTRL_MUXSEL6 0x160
#define HW_PINCTRL_MUXSEL7 0x170
#define HW_PINCTRL_DRIVE0 0x200
#define HW_PINCTRL_DRIVE1 0x210
#define HW_PINCTRL_DRIVE2 0x220
#define HW_PINCTRL_DRIVE3 0x230
#define HW_PINCTRL_DRIVE4 0x240
#define HW_PINCTRL_DRIVE5 0x250
#define HW_PINCTRL_DRIVE6 0x260
#define HW_PINCTRL_DRIVE7 0x270
#define HW_PINCTRL_DRIVE8 0x280
#define HW_PINCTRL_DRIVE9 0x290
#define HW_PINCTRL_DRIVE10 0x2A0
#define HW_PINCTRL_DRIVE11 0x2B0
#define HW_PINCTRL_DRIVE12 0x2C0
#define HW_PINCTRL_DRIVE13 0x2D0
#define HW_PINCTRL_DRIVE14 0x2E0
#define HW_PINCTRL_PULL0 0x300
#define HW_PINCTRL_PULL1 0x310
#define HW_PINCTRL_PULL2 0x320
#define HW_PINCTRL_PULL3 0x330
#define HW_PINCTRL_DOUT0 0x400
#define HW_PINCTRL_DOUT1 0x410
#define HW_PINCTRL_DOUT2 0x420
#define HW_PINCTRL_DIN0 0x500
#define HW_PINCTRL_DIN1 0x510
#define HW_PINCTRL_DIN2 0x520
#define HW_PINCTRL_DOE0 0x600
#define HW_PINCTRL_DOE1 0x610
#define HW_PINCTRL_DOE2 0x620
#define HW_PINCTRL_PIN2IRQ0 0x700
#define HW_PINCTRL_PIN2IRQ1 0x710
#define HW_PINCTRL_PIN2IRQ2 0x720
#define HW_PINCTRL_IRQEN0 0x800
#define HW_PINCTRL_IRQEN1 0x810
#define HW_PINCTRL_IRQEN2 0x820
#define HW_PINCTRL_IRQLEVEL0 0x900
#define HW_PINCTRL_IRQLEVEL1 0x910
#define HW_PINCTRL_IRQLEVEL2 0x920
#define HW_PINCTRL_IRQPOL0 0xA00
#define HW_PINCTRL_IRQPOL1 0xA10
#define HW_PINCTRL_IRQPOL2 0xA20
#define HW_PINCTRL_IRQSTAT0 0xB00
#define HW_PINCTRL_IRQSTAT1 0xB10
#define HW_PINCTRL_IRQSTAT2 0xB20
#endif
arch/arm/mach-stmp37xx/include/mach/regs-power.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: POWER register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_POWER
#define _MACH_REGS_POWER
#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
#define HW_POWER_CTRL 0x0
#define BM_POWER_CTRL_CLKGATE 0x40000000
#define HW_POWER_5VCTRL 0x10
#define HW_POWER_MINPWR 0x20
#define HW_POWER_CHARGE 0x30
#define HW_POWER_VDDDCTRL 0x40
#define HW_POWER_VDDACTRL 0x50
#define HW_POWER_VDDIOCTRL 0x60
#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
#define BP_POWER_VDDIOCTRL_TRG 0
#define HW_POWER_STS 0xB0
#define BM_POWER_STS_VBUSVALID 0x00000002
#define BM_POWER_STS_BVALID 0x00000004
#define BM_POWER_STS_AVALID 0x00000008
#define BM_POWER_STS_DC_OK 0x00000100
#define HW_POWER_RESET 0xE0
#define HW_POWER_DEBUG 0xF0
#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
#endif
arch/arm/mach-stmp37xx/include/mach/regs-pwm.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: PWM register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
#define HW_PWM_CTRL 0x0
#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
#define HW_PWM_ACTIVEn 0x10
#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
#define BP_PWM_ACTIVEn_ACTIVE 0
#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
#define BP_PWM_ACTIVEn_INACTIVE 16
#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
#define HW_PWM_PERIODn 0x20
#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
#define BP_PWM_PERIODn_PERIOD 0
#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
#define BP_PWM_PERIODn_ACTIVE_STATE 16
#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
#define BP_PWM_PERIODn_INACTIVE_STATE 18
#define BM_PWM_PERIODn_CDIV 0x00700000
#define BP_PWM_PERIODn_CDIV 20
arch/arm/mach-stmp37xx/include/mach/regs-rtc.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: RTC register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
#define REGS_RTC_PHYS 0x8005C000
#define REGS_RTC_SIZE 0x2000
#define HW_RTC_CTRL 0x0
#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
#define BP_RTC_CTRL_ALARM_IRQ_EN 0
#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
#define HW_RTC_STAT 0x10
#define BM_RTC_STAT_NEW_REGS 0x0000FF00
#define BP_RTC_STAT_NEW_REGS 8
#define BM_RTC_STAT_STALE_REGS 0x00FF0000
#define BP_RTC_STAT_STALE_REGS 16
#define BM_RTC_STAT_RTC_PRESENT 0x80000000
#define HW_RTC_SECONDS 0x30
#define HW_RTC_ALARM 0x40
#define HW_RTC_WATCHDOG 0x50
#define HW_RTC_PERSISTENT0 0x60
#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
#define HW_RTC_PERSISTENT1 0x70
#define HW_RTC_VERSION 0xD0
arch/arm/mach-stmp37xx/include/mach/regs-ssp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: SSP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
#define REGS_SSP1_PHYS 0x80010000
#define REGS_SSP2_PHYS 0x80034000
#define REGS_SSP_SIZE 0x2000
#define HW_SSP_CTRL0 0x0
#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_SSP_CTRL0_XFER_COUNT 0
#define BM_SSP_CTRL0_ENABLE 0x00010000
#define BM_SSP_CTRL0_GET_RESP 0x00020000
#define BM_SSP_CTRL0_LONG_RESP 0x00080000
#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
#define BP_SSP_CTRL0_BUS_WIDTH 22
#define BM_SSP_CTRL0_DATA_XFER 0x01000000
#define BM_SSP_CTRL0_READ 0x02000000
#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
#define BM_SSP_CTRL0_LOCK_CS 0x08000000
#define BM_SSP_CTRL0_RUN 0x20000000
#define BM_SSP_CTRL0_CLKGATE 0x40000000
#define BM_SSP_CTRL0_SFTRST 0x80000000
#define HW_SSP_CMD0 0x10
#define BM_SSP_CMD0_CMD 0x000000FF
#define BP_SSP_CMD0_CMD 0
#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
#define BP_SSP_CMD0_BLOCK_COUNT 8
#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
#define BP_SSP_CMD0_BLOCK_SIZE 16
#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
#define BP_SSP_CMD1_CMD_ARG 0
#define HW_SSP_TIMING 0x50
#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
#define BP_SSP_TIMING_CLOCK_RATE 0
#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
#define BP_SSP_TIMING_TIMEOUT 16
#define HW_SSP_CTRL1 0x60
#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
#define BP_SSP_CTRL1_SSP_MODE 0
#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
#define BP_SSP_CTRL1_WORD_LENGTH 4
#define BM_SSP_CTRL1_POLARITY 0x00000200
#define BM_SSP_CTRL1_PHASE 0x00000400
#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
#define HW_SSP_DATA 0x70
#define HW_SSP_SDRESP0 0x80
#define HW_SSP_SDRESP1 0x90
#define HW_SSP_SDRESP2 0xA0
#define HW_SSP_SDRESP3 0xB0
#define HW_SSP_STATUS 0xC0
#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
#define BM_SSP_STATUS_TIMEOUT 0x00001000
#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
#define BM_SSP_STATUS_RESP_ERR 0x00008000
#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
#define BM_SSP_STATUS_CARD_DETECT 0x10000000
arch/arm/mach-stmp37xx/include/mach/regs-timrot.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: TIMROT register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MACH_REGS_TIMROT
#define _MACH_REGS_TIMROT
#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
#define HW_TIMROT_ROTCTRL 0x0
#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
#define HW_TIMROT_TIMCTRLn 0x20
#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
#define BP_TIMROT_TIMCTRLn_SELECT 0
#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
#define BP_TIMROT_TIMCTRLn_PRESCALE 4
#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
#define HW_TIMROT_TIMCOUNTn 0x30
#endif
arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: UARTAPP register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
#define REGS_UARTAPP1_PHYS 0x8006C000
#define REGS_UARTAPP_SIZE 0x2000
#define HW_UARTAPP_CTRL0 0x0
#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_UARTAPP_CTRL0_XFER_COUNT 0
#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
#define BM_UARTAPP_CTRL0_RUN 0x20000000
#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
#define BP_UARTAPP_CTRL1_XFER_COUNT 0
#define BM_UARTAPP_CTRL1_RUN 0x10000000
#define HW_UARTAPP_CTRL2 0x20
#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
#define BP_UARTAPP_CTRL2_UARTEN 0
#define BM_UARTAPP_CTRL2_TXE 0x00000100
#define BM_UARTAPP_CTRL2_RXE 0x00000200
#define BM_UARTAPP_CTRL2_RTS 0x00000800
#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
#define HW_UARTAPP_LINECTRL 0x30
#define BM_UARTAPP_LINECTRL_BRK 0x00000001
#define BP_UARTAPP_LINECTRL_BRK 0
#define BM_UARTAPP_LINECTRL_PEN 0x00000002
#define BM_UARTAPP_LINECTRL_EPS 0x00000004
#define BM_UARTAPP_LINECTRL_STP2 0x00000008
#define BM_UARTAPP_LINECTRL_FEN 0x00000010
#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
#define BP_UARTAPP_LINECTRL_WLEN 5
#define BM_UARTAPP_LINECTRL_SPS 0x00000080
#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
#define HW_UARTAPP_INTR 0x50
#define BM_UARTAPP_INTR_CTSMIS 0x00000002
#define BM_UARTAPP_INTR_RTIS 0x00000040
#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
#define BM_UARTAPP_INTR_RXIEN 0x00100000
#define BM_UARTAPP_INTR_RTIEN 0x00400000
#define HW_UARTAPP_DATA 0x60
#define HW_UARTAPP_STAT 0x70
#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
#define BP_UARTAPP_STAT_RXCOUNT 0
#define BM_UARTAPP_STAT_FERR 0x00010000
#define BM_UARTAPP_STAT_PERR 0x00020000
#define BM_UARTAPP_STAT_BERR 0x00040000
#define BM_UARTAPP_STAT_OERR 0x00080000
#define BM_UARTAPP_STAT_RXFE 0x01000000
#define BM_UARTAPP_STAT_TXFF 0x02000000
#define BM_UARTAPP_STAT_TXFE 0x08000000
#define BM_UARTAPP_STAT_CTS 0x10000000
#define HW_UARTAPP_VERSION 0x90
arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp378x: UARTDBG register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
#define REGS_UARTDBG_PHYS 0x80070000
#define REGS_UARTDBG_SIZE 0x2000
#define HW_UARTDBGDR 0x00000000
#define BP_UARTDBGDR_UNAVAILABLE 16
#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGDR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
#define BP_UARTDBGDR_RESERVED 12
#define BM_UARTDBGDR_RESERVED 0x0000F000
#define BF_UARTDBGDR_RESERVED(v) \
(((v) << 12) & BM_UARTDBGDR_RESERVED)
#define BM_UARTDBGDR_OE 0x00000800
#define BM_UARTDBGDR_BE 0x00000400
#define BM_UARTDBGDR_PE 0x00000200
#define BM_UARTDBGDR_FE 0x00000100
#define BP_UARTDBGDR_DATA 0
#define BM_UARTDBGDR_DATA 0x000000FF
#define BF_UARTDBGDR_DATA(v) \
(((v) << 0) & BM_UARTDBGDR_DATA)
#define HW_UARTDBGRSR_ECR 0x00000004
#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
#define BP_UARTDBGRSR_ECR_EC 4
#define BM_UARTDBGRSR_ECR_EC 0x000000F0
#define BF_UARTDBGRSR_ECR_EC(v) \
(((v) << 4) & BM_UARTDBGRSR_ECR_EC)
#define BM_UARTDBGRSR_ECR_OE 0x00000008
#define BM_UARTDBGRSR_ECR_BE 0x00000004
#define BM_UARTDBGRSR_ECR_PE 0x00000002
#define BM_UARTDBGRSR_ECR_FE 0x00000001
#define HW_UARTDBGFR 0x00000018
#define BP_UARTDBGFR_UNAVAILABLE 16
#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGFR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
#define BP_UARTDBGFR_RESERVED 9
#define BM_UARTDBGFR_RESERVED 0x0000FE00
#define BF_UARTDBGFR_RESERVED(v) \
(((v) << 9) & BM_UARTDBGFR_RESERVED)
#define BM_UARTDBGFR_RI 0x00000100
#define BM_UARTDBGFR_TXFE 0x00000080
#define BM_UARTDBGFR_RXFF 0x00000040
#define BM_UARTDBGFR_TXFF 0x00000020
#define BM_UARTDBGFR_RXFE 0x00000010
#define BM_UARTDBGFR_BUSY 0x00000008
#define BM_UARTDBGFR_DCD 0x00000004
#define BM_UARTDBGFR_DSR 0x00000002
#define BM_UARTDBGFR_CTS 0x00000001
#define HW_UARTDBGILPR 0x00000020
#define BP_UARTDBGILPR_UNAVAILABLE 8
#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGILPR_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
#define BP_UARTDBGILPR_ILPDVSR 0
#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
#define BF_UARTDBGILPR_ILPDVSR(v) \
(((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
#define HW_UARTDBGIBRD 0x00000024
#define BP_UARTDBGIBRD_UNAVAILABLE 16
#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
#define BP_UARTDBGIBRD_BAUD_DIVINT 0
#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
(((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
#define HW_UARTDBGFBRD 0x00000028
#define BP_UARTDBGFBRD_UNAVAILABLE 8
#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
(((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
#define BP_UARTDBGFBRD_RESERVED 6
#define BM_UARTDBGFBRD_RESERVED 0x000000C0
#define BF_UARTDBGFBRD_RESERVED(v) \
(((v) << 6) & BM_UARTDBGFBRD_RESERVED)
#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
(((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
#define HW_UARTDBGLCR_H 0x0000002c
#define BP_UARTDBGLCR_H_UNAVAILABLE 16
#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
#define BP_UARTDBGLCR_H_RESERVED 8
#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
#define BF_UARTDBGLCR_H_RESERVED(v) \
(((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
#define BM_UARTDBGLCR_H_SPS 0x00000080
#define BP_UARTDBGLCR_H_WLEN 5
#define BM_UARTDBGLCR_H_WLEN 0x00000060
#define BF_UARTDBGLCR_H_WLEN(v) \
(((v) << 5) & BM_UARTDBGLCR_H_WLEN)
#define BM_UARTDBGLCR_H_FEN 0x00000010
#define BM_UARTDBGLCR_H_STP2 0x00000008
#define BM_UARTDBGLCR_H_EPS 0x00000004
#define BM_UARTDBGLCR_H_PEN 0x00000002
#define BM_UARTDBGLCR_H_BRK 0x00000001
#define HW_UARTDBGCR 0x00000030
#define BP_UARTDBGCR_UNAVAILABLE 16
#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGCR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
#define BM_UARTDBGCR_CTSEN 0x00008000
#define BM_UARTDBGCR_RTSEN 0x00004000
#define BM_UARTDBGCR_OUT2 0x00002000
#define BM_UARTDBGCR_OUT1 0x00001000
#define BM_UARTDBGCR_RTS 0x00000800
#define BM_UARTDBGCR_DTR 0x00000400
#define BM_UARTDBGCR_RXE 0x00000200
#define BM_UARTDBGCR_TXE 0x00000100
#define BM_UARTDBGCR_LBE 0x00000080
#define BP_UARTDBGCR_RESERVED 3
#define BM_UARTDBGCR_RESERVED 0x00000078
#define BF_UARTDBGCR_RESERVED(v) \
(((v) << 3) & BM_UARTDBGCR_RESERVED)
#define BM_UARTDBGCR_SIRLP 0x00000004
#define BM_UARTDBGCR_SIREN 0x00000002
#define BM_UARTDBGCR_UARTEN 0x00000001
#define HW_UARTDBGIFLS 0x00000034
#define BP_UARTDBGIFLS_UNAVAILABLE 16
#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
#define BP_UARTDBGIFLS_RESERVED 6
#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
#define BF_UARTDBGIFLS_RESERVED(v) \
(((v) << 6) & BM_UARTDBGIFLS_RESERVED)
#define BP_UARTDBGIFLS_RXIFLSEL 3
#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
#define BF_UARTDBGIFLS_RXIFLSEL(v) \
(((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
#define BP_UARTDBGIFLS_TXIFLSEL 0
#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
#define BF_UARTDBGIFLS_TXIFLSEL(v) \
(((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
#define HW_UARTDBGIMSC 0x00000038
#define BP_UARTDBGIMSC_UNAVAILABLE 16
#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
#define BP_UARTDBGIMSC_RESERVED 11
#define BM_UARTDBGIMSC_RESERVED 0x0000F800
#define BF_UARTDBGIMSC_RESERVED(v) \
(((v) << 11) & BM_UARTDBGIMSC_RESERVED)
#define BM_UARTDBGIMSC_OEIM 0x00000400
#define BM_UARTDBGIMSC_BEIM 0x00000200
#define BM_UARTDBGIMSC_PEIM 0x00000100
#define BM_UARTDBGIMSC_FEIM 0x00000080
#define BM_UARTDBGIMSC_RTIM 0x00000040
#define BM_UARTDBGIMSC_TXIM 0x00000020
#define BM_UARTDBGIMSC_RXIM 0x00000010
#define BM_UARTDBGIMSC_DSRMIM 0x00000008
#define BM_UARTDBGIMSC_DCDMIM 0x00000004
#define BM_UARTDBGIMSC_CTSMIM 0x00000002
#define BM_UARTDBGIMSC_RIMIM 0x00000001
#define HW_UARTDBGRIS 0x0000003c
#define BP_UARTDBGRIS_UNAVAILABLE 16
#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGRIS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
#define BP_UARTDBGRIS_RESERVED 11
#define BM_UARTDBGRIS_RESERVED 0x0000F800
#define BF_UARTDBGRIS_RESERVED(v) \
(((v) << 11) & BM_UARTDBGRIS_RESERVED)
#define BM_UARTDBGRIS_OERIS 0x00000400
#define BM_UARTDBGRIS_BERIS 0x00000200
#define BM_UARTDBGRIS_PERIS 0x00000100
#define BM_UARTDBGRIS_FERIS 0x00000080
#define BM_UARTDBGRIS_RTRIS 0x00000040
#define BM_UARTDBGRIS_TXRIS 0x00000020
#define BM_UARTDBGRIS_RXRIS 0x00000010
#define BM_UARTDBGRIS_DSRRMIS 0x00000008
#define BM_UARTDBGRIS_DCDRMIS 0x00000004
#define BM_UARTDBGRIS_CTSRMIS 0x00000002
#define BM_UARTDBGRIS_RIRMIS 0x00000001
#define HW_UARTDBGMIS 0x00000040
#define BP_UARTDBGMIS_UNAVAILABLE 16
#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGMIS_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
#define BP_UARTDBGMIS_RESERVED 11
#define BM_UARTDBGMIS_RESERVED 0x0000F800
#define BF_UARTDBGMIS_RESERVED(v) \
(((v) << 11) & BM_UARTDBGMIS_RESERVED)
#define BM_UARTDBGMIS_OEMIS 0x00000400
#define BM_UARTDBGMIS_BEMIS 0x00000200
#define BM_UARTDBGMIS_PEMIS 0x00000100
#define BM_UARTDBGMIS_FEMIS 0x00000080
#define BM_UARTDBGMIS_RTMIS 0x00000040
#define BM_UARTDBGMIS_TXMIS 0x00000020
#define BM_UARTDBGMIS_RXMIS 0x00000010
#define BM_UARTDBGMIS_DSRMMIS 0x00000008
#define BM_UARTDBGMIS_DCDMMIS 0x00000004
#define BM_UARTDBGMIS_CTSMMIS 0x00000002
#define BM_UARTDBGMIS_RIMMIS 0x00000001
#define HW_UARTDBGICR 0x00000044
#define BP_UARTDBGICR_UNAVAILABLE 16
#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGICR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
#define BP_UARTDBGICR_RESERVED 11
#define BM_UARTDBGICR_RESERVED 0x0000F800
#define BF_UARTDBGICR_RESERVED(v) \
(((v) << 11) & BM_UARTDBGICR_RESERVED)
#define BM_UARTDBGICR_OEIC 0x00000400
#define BM_UARTDBGICR_BEIC 0x00000200
#define BM_UARTDBGICR_PEIC 0x00000100
#define BM_UARTDBGICR_FEIC 0x00000080
#define BM_UARTDBGICR_RTIC 0x00000040
#define BM_UARTDBGICR_TXIC 0x00000020
#define BM_UARTDBGICR_RXIC 0x00000010
#define BM_UARTDBGICR_DSRMIC 0x00000008
#define BM_UARTDBGICR_DCDMIC 0x00000004
#define BM_UARTDBGICR_CTSMIC 0x00000002
#define BM_UARTDBGICR_RIMIC 0x00000001
#define HW_UARTDBGDMACR 0x00000048
#define BP_UARTDBGDMACR_UNAVAILABLE 16
#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
(((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
#define BP_UARTDBGDMACR_RESERVED 3
#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
#define BF_UARTDBGDMACR_RESERVED(v) \
(((v) << 3) & BM_UARTDBGDMACR_RESERVED)
#define BM_UARTDBGDMACR_DMAONERR 0x00000004
#define BM_UARTDBGDMACR_TXDMAE 0x00000002
#define BM_UARTDBGDMACR_RXDMAE 0x00000001
arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: USBCTL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
#define REGS_USBCTL_PHYS 0x80000
arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: USBCTRL register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
#define REGS_USBCTRL_PHYS 0x80080000
arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h deleted 100644 → 0
View file @ e8765afe
/*
* stmp37xx: USBPHY register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
#define HW_USBPHY_PWD 0x0
#define HW_USBPHY_CTRL 0x30
#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
#define BM_USBPHY_CTRL_CLKGATE 0x40000000
#define BM_USBPHY_CTRL_SFTRST 0x80000000
#define HW_USBPHY_STATUS 0x40
#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
arch/arm/mach-stmp37xx/stmp37xx.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX platform support
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/stmp3xxx.h>
#include <mach/dma.h>
#include <mach/platform.h>
#include <mach/regs-icoll.h>
#include <mach/regs-apbh.h>
#include <mach/regs-apbx.h>
#include "stmp37xx.h"
/*
* IRQ handling
*/
static void stmp37xx_ack_irq(struct irq_data *d)
{
/* Disable IRQ */
stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
/* ACK current interrupt */
__raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
/* Barrier */
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}
static void stmp37xx_mask_irq(struct irq_data *d)
{
/* IRQ disable */
stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
}
static void stmp37xx_unmask_irq(struct irq_data *d)
{
/* IRQ enable */
stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
}
static struct irq_chip stmp37xx_chip = {
.irq_ack = stmp37xx_ack_irq,
.irq_mask = stmp37xx_mask_irq,
.irq_unmask = stmp37xx_unmask_irq,
};
void __init stmp37xx_init_irq(void)
{
stmp3xxx_init_irq(&stmp37xx_chip);
}
/*
* DMA interrupt handling
*/
void stmp3xxx_arch_dma_enable_interrupt(int channel)
{
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
REGS_APBH_BASE + HW_APBH_CTRL1);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
REGS_APBX_BASE + HW_APBX_CTRL1);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
void stmp3xxx_arch_dma_clear_interrupt(int channel)
{
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
REGS_APBH_BASE + HW_APBH_CTRL1);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
REGS_APBX_BASE + HW_APBX_CTRL1);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
int stmp3xxx_arch_dma_is_interrupt(int channel)
{
int r = 0;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
case STMP3XXX_BUS_APBX:
r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
(1 << STMP3XXX_DMA_CHANNEL(channel));
break;
}
return r;
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
void stmp3xxx_arch_dma_reset_channel(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
/* Reset channel and wait for it to complete */
stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
REGS_APBH_BASE + HW_APBH_CTRL0);
while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
(chbit << BP_APBH_CTRL0_RESET_CHANNEL))
cpu_relax();
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
REGS_APBX_BASE + HW_APBX_CTRL0);
while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
(chbit << BP_APBX_CTRL0_RESET_CHANNEL))
cpu_relax();
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
void stmp3xxx_arch_dma_freeze(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
void stmp3xxx_arch_dma_unfreeze(int channel)
{
unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
case STMP3XXX_BUS_APBX:
stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
break;
}
}
EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
/*
* The registers are all very closely mapped, so we might as well map them all
* with a single mapping
*
* Logical Physical
* f0000000 80000000 On-chip registers
* f1000000 00000000 32k on-chip SRAM
*/
static struct map_desc stmp37xx_io_desc[] __initdata = {
{
.virtual = (u32)STMP3XXX_REGS_BASE,
.pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
.length = SZ_1M,
.type = MT_DEVICE
},
{
.virtual = (u32)STMP3XXX_OCRAM_BASE,
.pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
.length = STMP3XXX_OCRAM_SIZE,
.type = MT_DEVICE,
},
};
void __init stmp37xx_map_io(void)
{
iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
}
arch/arm/mach-stmp37xx/stmp37xx.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X internal functions and data declarations
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_STMP37XX_H
#define __MACH_STMP37XX_H
void stmp37xx_map_io(void);
void stmp37xx_init_irq(void);
#endif /* __MACH_STMP37XX_H */
arch/arm/mach-stmp37xx/stmp37xx_devb.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX development board support
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/stmp3xxx.h>
#include <mach/pins.h>
#include <mach/pinmux.h>
#include "stmp37xx.h"
/*
* List of STMP37xx development board specific devices
*/
static struct platform_device *stmp37xx_devb_devices[] = {
&stmp3xxx_dbguart,
&stmp3xxx_appuart,
};
static struct pin_desc dbguart_pins_0[] = {
{ PINID_PWM0, PIN_FUN3, },
{ PINID_PWM1, PIN_FUN3, },
};
struct pin_desc appuart_pins_0[] = {
{ PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
{ PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
};
static struct pin_group appuart_pins[] = {
[0] = {
.pins = appuart_pins_0,
.nr_pins = ARRAY_SIZE(appuart_pins_0),
},
/* 37xx has the only app uart */
};
static struct pin_group dbguart_pins[] = {
[0] = {
.pins = dbguart_pins_0,
.nr_pins = ARRAY_SIZE(dbguart_pins_0),
},
};
static int dbguart_pins_control(int id, int request)
{
int r = 0;
if (request)
r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
else
stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
return r;
}
static void __init stmp37xx_devb_init(void)
{
stmp3xxx_pinmux_init(NR_REAL_IRQS);
/* Init STMP3xxx platform */
stmp3xxx_init();
stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
stmp3xxx_appuart.dev.platform_data = appuart_pins;
/* Add STMP37xx development board devices */
platform_add_devices(stmp37xx_devb_devices,
ARRAY_SIZE(stmp37xx_devb_devices));
}
MACHINE_START(STMP37XX, "STMP37XX")
.boot_params = 0x40000100,
.map_io = stmp37xx_map_io,
.init_irq = stmp37xx_init_irq,
.timer = &stmp3xxx_timer,
.init_machine = stmp37xx_devb_init,
MACHINE_END
arch/arm/mach-tegra/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-tegra/platsmp.c
View file @ 4b60e5f9
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
...@@ -122,6 +123,8 @@ void __init smp_init_cpus(void) ...@@ -122,6 +123,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
cpu_set(i, cpu_possible_map); cpu_set(i, cpu_possible_map);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-ux500/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
/*
* This file is based ARM realview platform.
* Copyright (C) ARM Limited.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef ASMARM_ARCH_SMP_H
#define ASMARM_ARCH_SMP_H
#include <asm/hardware/gic.h>
/* This is required to wakeup the secondary core */
extern void u8500_secondary_startup(void);
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-ux500/platsmp.c
View file @ 4b60e5f9
...@@ -18,10 +18,14 @@ ...@@ -18,10 +18,14 @@
#include <linux/io.h> #include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/setup.h> #include <mach/setup.h>
/* This is called from headsmp.S to wakeup the secondary core */
extern void u8500_secondary_startup(void);
/* /*
* control for which core is the next to come out of the secondary * control for which core is the next to come out of the secondary
* boot "holding pen" * boot "holding pen"
...@@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/ */
write_pen_release(cpu); write_pen_release(cpu);
smp_cross_call(cpumask_of(cpu), 1); gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
...@@ -162,6 +166,8 @@ void __init smp_init_cpus(void) ...@@ -162,6 +166,8 @@ void __init smp_init_cpus(void)
for (i = 0; i < ncores; i++) for (i = 0; i < ncores; i++)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
......
arch/arm/mach-versatile/core.c
View file @ 4b60e5f9
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/gfp.h> #include <linux/gfp.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/mtd/physmap.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/irq.h> #include <asm/irq.h>
...@@ -42,7 +43,6 @@ ...@@ -42,7 +43,6 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h> #include <asm/mach/irq.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
...@@ -190,27 +190,7 @@ void __init versatile_map_io(void) ...@@ -190,27 +190,7 @@ void __init versatile_map_io(void)
#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
static int versatile_flash_init(void) static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
val = __raw_readl(VERSATILE_FLASHCTRL);
val &= ~VERSATILE_FLASHPROG_FLVPPEN;
__raw_writel(val, VERSATILE_FLASHCTRL);
return 0;
}
static void versatile_flash_exit(void)
{
u32 val;
val = __raw_readl(VERSATILE_FLASHCTRL);
val &= ~VERSATILE_FLASHPROG_FLVPPEN;
__raw_writel(val, VERSATILE_FLASHCTRL);
}
static void versatile_flash_set_vpp(int on)
{ {
u32 val; u32 val;
...@@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on) ...@@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on)
__raw_writel(val, VERSATILE_FLASHCTRL); __raw_writel(val, VERSATILE_FLASHCTRL);
} }
static struct flash_platform_data versatile_flash_data = { static struct physmap_flash_data versatile_flash_data = {
.map_name = "cfi_probe",
.width = 4, .width = 4,
.init = versatile_flash_init,
.exit = versatile_flash_exit,
.set_vpp = versatile_flash_set_vpp, .set_vpp = versatile_flash_set_vpp,
}; };
...@@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = { ...@@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = {
}; };
static struct platform_device versatile_flash_device = { static struct platform_device versatile_flash_device = {
.name = "armflash", .name = "physmap-flash",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &versatile_flash_data, .platform_data = &versatile_flash_data,
......
arch/arm/mach-vexpress/ct-ca9x4.c
View file @ 4b60e5f9
...@@ -223,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void) ...@@ -223,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void)
for (i = 0; i < ncores; ++i) for (i = 0; i < ncores; ++i)
set_cpu_possible(i, true); set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
} }
static void ct_ca9x4_smp_enable(unsigned int max_cpus) static void ct_ca9x4_smp_enable(unsigned int max_cpus)
......
arch/arm/mach-vexpress/include/mach/smp.h deleted 100644 → 0
View file @ e8765afe
#ifndef __MACH_SMP_H
#define __MACH_SMP_H
#include <asm/hardware/gic.h>
/*
* We use IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/mach-vexpress/v2m.c
View file @ 4b60e5f9
...@@ -13,11 +13,11 @@ ...@@ -13,11 +13,11 @@
#include <linux/sysdev.h> #include <linux/sysdev.h>
#include <linux/usb/isp1760.h> #include <linux/usb/isp1760.h>
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/mtd/physmap.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/sizes.h> #include <asm/sizes.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <asm/mach/time.h> #include <asm/mach/time.h>
#include <asm/hardware/arm_timer.h> #include <asm/hardware/arm_timer.h>
...@@ -207,27 +207,13 @@ static struct platform_device v2m_usb_device = { ...@@ -207,27 +207,13 @@ static struct platform_device v2m_usb_device = {
.dev.platform_data = &v2m_usb_config, .dev.platform_data = &v2m_usb_config,
}; };
static int v2m_flash_init(void) static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
writel(0, MMIO_P2V(V2M_SYS_FLASH));
return 0;
}
static void v2m_flash_exit(void)
{
writel(0, MMIO_P2V(V2M_SYS_FLASH));
}
static void v2m_flash_set_vpp(int on)
{ {
writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
} }
static struct flash_platform_data v2m_flash_data = { static struct physmap_flash_data v2m_flash_data = {
.map_name = "cfi_probe",
.width = 4, .width = 4,
.init = v2m_flash_init,
.exit = v2m_flash_exit,
.set_vpp = v2m_flash_set_vpp, .set_vpp = v2m_flash_set_vpp,
}; };
...@@ -244,7 +230,7 @@ static struct resource v2m_flash_resources[] = { ...@@ -244,7 +230,7 @@ static struct resource v2m_flash_resources[] = {
}; };
static struct platform_device v2m_flash_device = { static struct platform_device v2m_flash_device = {
.name = "armflash", .name = "physmap-flash",
.id = -1, .id = -1,
.resource = v2m_flash_resources, .resource = v2m_flash_resources,
.num_resources = ARRAY_SIZE(v2m_flash_resources), .num_resources = ARRAY_SIZE(v2m_flash_resources),
......
arch/arm/mm/init.c
View file @ 4b60e5f9
...@@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn, ...@@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
} }
} }
#ifdef CONFIG_ZONE_DMA
static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
unsigned long dma_size)
{
if (size[0] <= dma_size)
return;
size[ZONE_NORMAL] = size[0] - dma_size;
size[ZONE_DMA] = dma_size;
hole[ZONE_NORMAL] = hole[0];
hole[ZONE_DMA] = 0;
}
#endif
static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
unsigned long max_high) unsigned long max_high)
{ {
...@@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, ...@@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
#endif #endif
} }
#ifdef ARM_DMA_ZONE_SIZE
#ifndef CONFIG_ZONE_DMA
#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations
#endif
/* /*
* Adjust the sizes according to any special requirements for * Adjust the sizes according to any special requirements for
* this machine type. * this machine type.
*/ */
arch_adjust_zones(zone_size, zhole_size); arm_adjust_dma_zone(zone_size, zhole_size,
ARM_DMA_ZONE_SIZE >> PAGE_SHIFT);
#endif
free_area_init_node(0, zone_size, min, zhole_size); free_area_init_node(0, zone_size, min, zhole_size);
} }
......
arch/arm/plat-omap/include/plat/flash.h
View file @ 4b60e5f9
...@@ -11,6 +11,6 @@ ...@@ -11,6 +11,6 @@
#include <linux/mtd/map.h> #include <linux/mtd/map.h>
extern void omap1_set_vpp(struct map_info *map, int enable); extern void omap1_set_vpp(struct platform_device *pdev, int enable);
#endif #endif
arch/arm/plat-omap/include/plat/smp.h deleted 100644 → 0
View file @ e8765afe
/*
* OMAP4 machine specific smp.h
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Author:
* Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Interface functions needed for the SMP. This file is based on arm
* realview smp platform.
* Copyright (c) 2003 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef OMAP_ARCH_SMP_H
#define OMAP_ARCH_SMP_H
#include <asm/hardware/gic.h>
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
extern u32 omap_read_auxcoreboot0(void);
/*
* We use Soft IRQ1 as the IPI
*/
static inline void smp_cross_call(const struct cpumask *mask, int ipi)
{
gic_raise_softirq(mask, ipi);
}
#endif
arch/arm/plat-stmp3xxx/Kconfig deleted 100644 → 0
View file @ e8765afe
if ARCH_STMP3XXX
menu "Freescale STMP3xxx implementations"
choice
prompt "Select STMP3xxx chip family"
config ARCH_STMP37XX
bool "Freescale SMTP37xx"
select CPU_ARM926T
---help---
STMP37xx refers to 3700 through 3769 chips
config ARCH_STMP378X
bool "Freescale STMP378x"
select CPU_ARM926T
---help---
STMP378x refers to 3780 through 3789 chips
endchoice
choice
prompt "Select STMP3xxx board type"
config MACH_STMP37XX
depends on ARCH_STMP37XX
bool "Freescale STMP37xx development board"
config MACH_STMP378X
depends on ARCH_STMP378X
bool "Freescale STMP378x development board"
endchoice
endmenu
endif
arch/arm/plat-stmp3xxx/Makefile deleted 100644 → 0
View file @ e8765afe
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
arch/arm/plat-stmp3xxx/clock.c deleted 100644 → 0
View file @ e8765afe
/*
* Clock manipulation routines for Freescale STMP37XX/STMP378X
*
* Author: Vitaly Wool <vital@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define DEBUG
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/mach-types.h>
#include <mach/platform.h>
#include <mach/regs-clkctrl.h>
#include "clock.h"
static DEFINE_SPINLOCK(clocks_lock);
static struct clk osc_24M;
static struct clk pll_clk;
static struct clk cpu_clk;
static struct clk hclk;
static int propagate_rate(struct clk *);
static inline int clk_is_busy(struct clk *clk)
{
return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
}
static inline int clk_good(struct clk *clk)
{
return clk && !IS_ERR(clk) && clk->ops;
}
static int std_clk_enable(struct clk *clk)
{
if (clk->enable_reg) {
u32 clk_reg = __raw_readl(clk->enable_reg);
if (clk->enable_negate)
clk_reg &= ~(1 << clk->enable_shift);
else
clk_reg |= (1 << clk->enable_shift);
__raw_writel(clk_reg, clk->enable_reg);
if (clk->enable_wait)
udelay(clk->enable_wait);
return 0;
} else
return -EINVAL;
}
static int std_clk_disable(struct clk *clk)
{
if (clk->enable_reg) {
u32 clk_reg = __raw_readl(clk->enable_reg);
if (clk->enable_negate)
clk_reg |= (1 << clk->enable_shift);
else
clk_reg &= ~(1 << clk->enable_shift);
__raw_writel(clk_reg, clk->enable_reg);
return 0;
} else
return -EINVAL;
}
static int io_set_rate(struct clk *clk, u32 rate)
{
u32 reg_frac, clkctrl_frac;
int i, ret = 0, mask = 0x1f;
clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
if (clkctrl_frac < 18 || clkctrl_frac > 35) {
ret = -EINVAL;
goto out;
}
reg_frac = __raw_readl(clk->scale_reg);
reg_frac &= ~(mask << clk->scale_shift);
__raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
clk->scale_reg);
if (clk->busy_reg) {
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
if (!i)
ret = -ETIMEDOUT;
else
ret = 0;
}
out:
return ret;
}
static long io_get_rate(struct clk *clk)
{
long rate = clk->parent->rate * 18;
int mask = 0x1f;
rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
clk->rate = rate;
return rate;
}
static long per_get_rate(struct clk *clk)
{
long rate = clk->parent->rate;
long div;
const int mask = 0xff;
if (clk->enable_reg &&
!(__raw_readl(clk->enable_reg) & clk->enable_shift))
clk->rate = 0;
else {
div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
if (div)
rate /= div;
clk->rate = rate;
}
return clk->rate;
}
static int per_set_rate(struct clk *clk, u32 rate)
{
int ret = -EINVAL;
int div = (clk->parent->rate + rate - 1) / rate;
u32 reg_frac;
const int mask = 0xff;
int try = 10;
int i = -1;
if (div == 0 || div > mask)
goto out;
reg_frac = __raw_readl(clk->scale_reg);
reg_frac &= ~(mask << clk->scale_shift);
while (try--) {
__raw_writel(reg_frac | (div << clk->scale_shift),
clk->scale_reg);
if (clk->busy_reg) {
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
}
if (i)
break;
}
if (!i)
ret = -ETIMEDOUT;
else
ret = 0;
out:
if (ret != 0)
printk(KERN_ERR "%s: error %d\n", __func__, ret);
return ret;
}
static long lcdif_get_rate(struct clk *clk)
{
long rate = clk->parent->rate;
long div;
const int mask = 0xff;
div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
if (div) {
rate /= div;
div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
rate /= div;
}
clk->rate = rate;
return rate;
}
static int lcdif_set_rate(struct clk *clk, u32 rate)
{
int ret = 0;
/*
* On 3700, we can get most timings exact by modifying ref_pix
* and the divider, but keeping the phase timings at 1 (2
* phases per cycle).
*
* ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
* which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
*
* ns_cycle >= 2*18e3/(18*480) = 25/6
* ns_cycle <= 2*35e3/(18*480) = 875/108
*
* Multiply the ns_cycle by 'div' to lengthen it until it fits the
* bounds. This is the divider we'll use after ref_pix.
*
* 6 * ns_cycle >= 25 * div
* 108 * ns_cycle <= 875 * div
*/
u32 ns_cycle = 1000000 / rate;
u32 div, reg_val;
u32 lowest_result = (u32) -1;
u32 lowest_div = 0, lowest_fracdiv = 0;
for (div = 1; div < 256; ++div) {
u32 fracdiv;
u32 ps_result;
int lower_bound = 6 * ns_cycle >= 25 * div;
int upper_bound = 108 * ns_cycle <= 875 * div;
if (!lower_bound)
break;
if (!upper_bound)
continue;
/*
* Found a matching div. Calculate fractional divider needed,
* rounded up.
*/
fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
ns_cycle + 1000 * div - 1) /
(1000 * div);
if (fracdiv < 18 || fracdiv > 35) {
ret = -EINVAL;
goto out;
}
/* Calculate the actual cycle time this results in */
ps_result = 6250 * div * fracdiv / 27;
/* Use the fastest result that doesn't break ns_cycle */
if (ps_result <= lowest_result) {
lowest_result = ps_result;
lowest_div = div;
lowest_fracdiv = fracdiv;
}
}
if (div >= 256 || lowest_result == (u32) -1) {
ret = -EINVAL;
goto out;
}
pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
"PIXCLK=%uMHz cycle=%u.%03uns\n",
lowest_fracdiv, lowest_div,
480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
lowest_result / 1000, lowest_result % 1000);
/* Program ref_pix phase fractional divider */
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
/* Ungate PFD */
stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
/* Program pix divider */
reg_val = __raw_readl(clk->scale_reg);
reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
__raw_writel(reg_val, clk->scale_reg);
/* Wait for divider update */
if (clk->busy_reg) {
int i;
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
if (!i) {
ret = -ETIMEDOUT;
goto out;
}
}
/* Switch to ref_pix source */
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
out:
return ret;
}
static int cpu_set_rate(struct clk *clk, u32 rate)
{
u32 reg_val;
if (rate < 24000)
return -EINVAL;
else if (rate == 24000) {
/* switch to the 24M source */
clk_set_parent(clk, &osc_24M);
} else {
int i;
u32 clkctrl_cpu = 1;
u32 c = clkctrl_cpu;
u32 clkctrl_frac = 1;
u32 val;
for ( ; c < 0x40; c++) {
u32 f = (pll_clk.rate*18/c + rate/2) / rate;
int s1, s2;
if (f < 18 || f > 35)
continue;
s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
s2 = pll_clk.rate*18/c/f - rate;
pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
if (abs(s1) > abs(s2)) {
clkctrl_cpu = c;
clkctrl_frac = f;
}
if (s2 == 0)
break;
};
pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
clkctrl_cpu, clkctrl_frac);
if (c == 0x40) {
int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
rate;
if (abs(d) > 100 ||
clkctrl_frac < 18 || clkctrl_frac > 35)
return -EINVAL;
}
/* 4.6.2 */
val = __raw_readl(clk->scale_reg);
val &= ~(0x3f << clk->scale_shift);
val |= clkctrl_frac;
clk_set_parent(clk, &osc_24M);
udelay(10);
__raw_writel(val, clk->scale_reg);
/* ungate */
__raw_writel(1<<7, clk->scale_reg + 8);
/* write clkctrl_cpu */
clk->saved_div = clkctrl_cpu;
reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
reg_val &= ~0x3F;
reg_val |= clkctrl_cpu;
__raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
if (!i) {
printk(KERN_ERR "couldn't set up CPU divisor\n");
return -ETIMEDOUT;
}
clk_set_parent(clk, &pll_clk);
clk->saved_div = 0;
udelay(10);
}
return 0;
}
static long cpu_get_rate(struct clk *clk)
{
long rate = clk->parent->rate * 18;
rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
rate = ((rate + 9) / 10) * 10;
clk->rate = rate;
return rate;
}
static long cpu_round_rate(struct clk *clk, u32 rate)
{
unsigned long r = 0;
if (rate <= 24000)
r = 24000;
else {
u32 clkctrl_cpu = 1;
u32 clkctrl_frac;
do {
clkctrl_frac =
(pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
if (clkctrl_frac > 35)
continue;
if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
rate / 10)
break;
} while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
clkctrl_cpu--;
pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
clkctrl_cpu, clkctrl_frac);
if (clkctrl_frac < 18)
clkctrl_frac = 18;
if (clkctrl_frac > 35)
clkctrl_frac = 35;
r = pll_clk.rate * 18;
r /= clkctrl_frac;
r /= clkctrl_cpu;
r = 10 * ((r + 9) / 10);
}
return r;
}
static long emi_get_rate(struct clk *clk)
{
long rate = clk->parent->rate * 18;
rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
clk->rate = rate;
return rate;
}
static int clkseq_set_parent(struct clk *clk, struct clk *parent)
{
int ret = -EINVAL;
int shift = 8;
/* bypass? */
if (parent == &osc_24M)
shift = 4;
if (clk->bypass_reg) {
#ifdef CONFIG_ARCH_STMP378X
u32 hbus_val, cpu_val;
if (clk == &cpu_clk && shift == 4) {
hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_HBUS);
cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_CPU);
hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
BM_CLKCTRL_HBUS_DIV);
clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
cpu_val |= 1;
if (machine_is_stmp378x()) {
__raw_writel(hbus_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
__raw_writel(cpu_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
hclk.rate = 0;
}
} else if (clk == &cpu_clk && shift == 8) {
hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_HBUS);
cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
HW_CLKCTRL_CPU);
hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
BM_CLKCTRL_HBUS_DIV);
hbus_val |= 2;
cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
if (clk->saved_div)
cpu_val |= clk->saved_div;
else
cpu_val |= 2;
if (machine_is_stmp378x()) {
__raw_writel(hbus_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
__raw_writel(cpu_val,
REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
hclk.rate = 0;
}
}
#endif
__raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
ret = 0;
}
return ret;
}
static int hbus_set_rate(struct clk *clk, u32 rate)
{
u8 div = 0;
int is_frac = 0;
u32 clkctrl_hbus;
struct clk *parent = clk->parent;
pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
parent->rate);
if (rate > parent->rate)
return -EINVAL;
if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
parent->rate / rate < 32) {
pr_debug("%s: switching to fractional mode\n", __func__);
is_frac = 1;
}
if (is_frac)
div = (32 * rate + parent->rate / 2) / parent->rate;
else
div = (parent->rate + rate - 1) / rate;
pr_debug("%s: div calculated is %d\n", __func__, div);
if (!div || div > 0x1f)
return -EINVAL;
clk_set_parent(&cpu_clk, &osc_24M);
udelay(10);
clkctrl_hbus = __raw_readl(clk->scale_reg);
clkctrl_hbus &= ~0x3f;
clkctrl_hbus |= div;
clkctrl_hbus |= (is_frac << 5);
__raw_writel(clkctrl_hbus, clk->scale_reg);
if (clk->busy_reg) {
int i;
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
if (!i) {
printk(KERN_ERR "couldn't set up CPU divisor\n");
return -ETIMEDOUT;
}
}
clk_set_parent(&cpu_clk, &pll_clk);
__raw_writel(clkctrl_hbus, clk->scale_reg);
udelay(10);
return 0;
}
static long hbus_get_rate(struct clk *clk)
{
long rate = clk->parent->rate;
if (__raw_readl(clk->scale_reg) & 0x20) {
rate *= __raw_readl(clk->scale_reg) & 0x1f;
rate /= 32;
} else
rate /= __raw_readl(clk->scale_reg) & 0x1f;
clk->rate = rate;
return rate;
}
static int xbus_set_rate(struct clk *clk, u32 rate)
{
u16 div = 0;
u32 clkctrl_xbus;
pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
clk->parent->rate);
div = (clk->parent->rate + rate - 1) / rate;
pr_debug("%s: div calculated is %d\n", __func__, div);
if (!div || div > 0x3ff)
return -EINVAL;
clkctrl_xbus = __raw_readl(clk->scale_reg);
clkctrl_xbus &= ~0x3ff;
clkctrl_xbus |= div;
__raw_writel(clkctrl_xbus, clk->scale_reg);
if (clk->busy_reg) {
int i;
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
break;
if (!i) {
printk(KERN_ERR "couldn't set up xbus divisor\n");
return -ETIMEDOUT;
}
}
return 0;
}
static long xbus_get_rate(struct clk *clk)
{
long rate = clk->parent->rate;
rate /= __raw_readl(clk->scale_reg) & 0x3ff;
clk->rate = rate;
return rate;
}
/* Clock ops */
static struct clk_ops std_ops = {
.enable = std_clk_enable,
.disable = std_clk_disable,
.get_rate = per_get_rate,
.set_rate = per_set_rate,
.set_parent = clkseq_set_parent,
};
static struct clk_ops min_ops = {
.enable = std_clk_enable,
.disable = std_clk_disable,
};
static struct clk_ops cpu_ops = {
.enable = std_clk_enable,
.disable = std_clk_disable,
.get_rate = cpu_get_rate,
.set_rate = cpu_set_rate,
.round_rate = cpu_round_rate,
.set_parent = clkseq_set_parent,
};
static struct clk_ops io_ops = {
.enable = std_clk_enable,
.disable = std_clk_disable,
.get_rate = io_get_rate,
.set_rate = io_set_rate,
};
static struct clk_ops hbus_ops = {
.get_rate = hbus_get_rate,
.set_rate = hbus_set_rate,
};
static struct clk_ops xbus_ops = {
.get_rate = xbus_get_rate,
.set_rate = xbus_set_rate,
};
static struct clk_ops lcdif_ops = {
.enable = std_clk_enable,
.disable = std_clk_disable,
.get_rate = lcdif_get_rate,
.set_rate = lcdif_set_rate,
.set_parent = clkseq_set_parent,
};
static struct clk_ops emi_ops = {
.get_rate = emi_get_rate,
};
/* List of on-chip clocks */
static struct clk osc_24M = {
.flags = FIXED_RATE | ENABLED,
.rate = 24000,
};
static struct clk pll_clk = {
.parent = &osc_24M,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
.enable_shift = 16,
.enable_wait = 10,
.flags = FIXED_RATE | ENABLED,
.rate = 480000,
.ops = &min_ops,
};
static struct clk cpu_clk = {
.parent = &pll_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 0,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 7,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
.busy_bit = 28,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &cpu_ops,
};
static struct clk io_clk = {
.parent = &pll_clk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.enable_shift = 31,
.enable_negate = 1,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 24,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &io_ops,
};
static struct clk hclk = {
.parent = &cpu_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 7,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
.busy_bit = 29,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &hbus_ops,
};
static struct clk xclk = {
.parent = &osc_24M,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
.busy_bit = 31,
.flags = RATE_PROPAGATES | ENABLED,
.ops = &xbus_ops,
};
static struct clk uart_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 31,
.enable_negate = 1,
.flags = ENABLED,
.ops = &min_ops,
};
static struct clk audio_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 30,
.enable_negate = 1,
.ops = &min_ops,
};
static struct clk pwm_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 29,
.enable_negate = 1,
.ops = &min_ops,
};
static struct clk dri_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 28,
.enable_negate = 1,
.ops = &min_ops,
};
static struct clk digctl_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 27,
.enable_negate = 1,
.ops = &min_ops,
};
static struct clk timer_clk = {
.parent = &xclk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
.enable_shift = 26,
.enable_negate = 1,
.flags = ENABLED,
.ops = &min_ops,
};
static struct clk lcdif_clk = {
.parent = &pll_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.busy_bit = 29,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 1,
.flags = NEEDS_SET_PARENT,
.ops = &lcdif_ops,
};
static struct clk ssp_clk = {
.parent = &io_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.busy_bit = 29,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
.enable_shift = 31,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 5,
.enable_negate = 1,
.flags = NEEDS_SET_PARENT,
.ops = &std_ops,
};
static struct clk gpmi_clk = {
.parent = &io_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.busy_bit = 29,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 4,
.flags = NEEDS_SET_PARENT,
.ops = &std_ops,
};
static struct clk spdif_clk = {
.parent = &pll_clk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
.enable_shift = 31,
.enable_negate = 1,
.ops = &min_ops,
};
static struct clk emi_clk = {
.parent = &pll_clk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
.enable_shift = 31,
.enable_negate = 1,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
.scale_shift = 8,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
.busy_bit = 28,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 6,
.flags = ENABLED,
.ops = &emi_ops,
};
static struct clk ir_clk = {
.parent = &io_clk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 3,
.ops = &min_ops,
};
static struct clk saif_clk = {
.parent = &pll_clk,
.scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.busy_bit = 29,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
.enable_shift = 31,
.enable_negate = 1,
.bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
.bypass_shift = 0,
.ops = &std_ops,
};
static struct clk usb_clk = {
.parent = &pll_clk,
.enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
.enable_shift = 18,
.enable_negate = 1,
.ops = &min_ops,
};
/* list of all the clocks */
static struct clk_lookup onchip_clks[] = {
{
.con_id = "osc_24M",
.clk = &osc_24M,
}, {
.con_id = "pll",
.clk = &pll_clk,
}, {
.con_id = "cpu",
.clk = &cpu_clk,
}, {
.con_id = "hclk",
.clk = &hclk,
}, {
.con_id = "xclk",
.clk = &xclk,
}, {
.con_id = "io",
.clk = &io_clk,
}, {
.con_id = "uart",
.clk = &uart_clk,
}, {
.con_id = "audio",
.clk = &audio_clk,
}, {
.con_id = "pwm",
.clk = &pwm_clk,
}, {
.con_id = "dri",
.clk = &dri_clk,
}, {
.con_id = "digctl",
.clk = &digctl_clk,
}, {
.con_id = "timer",
.clk = &timer_clk,
}, {
.con_id = "lcdif",
.clk = &lcdif_clk,
}, {
.con_id = "ssp",
.clk = &ssp_clk,
}, {
.con_id = "gpmi",
.clk = &gpmi_clk,
}, {
.con_id = "spdif",
.clk = &spdif_clk,
}, {
.con_id = "emi",
.clk = &emi_clk,
}, {
.con_id = "ir",
.clk = &ir_clk,
}, {
.con_id = "saif",
.clk = &saif_clk,
}, {
.con_id = "usb",
.clk = &usb_clk,
},
};
static int __init propagate_rate(struct clk *clk)
{
struct clk_lookup *cl;
for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
cl++) {
if (unlikely(!clk_good(cl->clk)))
continue;
if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
cl->clk->ops->get_rate(cl->clk);
if (cl->clk->flags & RATE_PROPAGATES)
propagate_rate(cl->clk);
}
}
return 0;
}
/* Exported API */
unsigned long clk_get_rate(struct clk *clk)
{
if (unlikely(!clk_good(clk)))
return 0;
if (clk->rate != 0)
return clk->rate;
if (clk->ops->get_rate != NULL)
return clk->ops->get_rate(clk);
return clk_get_rate(clk->parent);
}
EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
if (unlikely(!clk_good(clk)))
return 0;
if (clk->ops->round_rate)
return clk->ops->round_rate(clk, rate);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
static inline int close_enough(long rate1, long rate2)
{
return rate1 && !((rate2 - rate1) * 1000 / rate1);
}
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
if (unlikely(!clk_good(clk)))
goto out;
if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
goto out;
else if (!close_enough(clk->rate, rate)) {
ret = clk->ops->set_rate(clk, rate);
if (ret < 0)
goto out;
clk->rate = rate;
if (clk->flags & RATE_PROPAGATES)
propagate_rate(clk);
} else
ret = 0;
out:
return ret;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_enable(struct clk *clk)
{
unsigned long clocks_flags;
if (unlikely(!clk_good(clk)))
return -EINVAL;
if (clk->parent)
clk_enable(clk->parent);
spin_lock_irqsave(&clocks_lock, clocks_flags);
clk->usage++;
if (clk->ops && clk->ops->enable)
clk->ops->enable(clk);
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void local_clk_disable(struct clk *clk)
{
if (unlikely(!clk_good(clk)))
return;
if (clk->usage == 0 && clk->ops->disable)
clk->ops->disable(clk);
if (clk->parent)
local_clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long clocks_flags;
if (unlikely(!clk_good(clk)))
return;
spin_lock_irqsave(&clocks_lock, clocks_flags);
if ((--clk->usage) == 0 && clk->ops->disable)
clk->ops->disable(clk);
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
if (clk->parent)
clk_disable(clk->parent);
}
EXPORT_SYMBOL(clk_disable);
/* Some additional API */
int clk_set_parent(struct clk *clk, struct clk *parent)
{
int ret = -ENODEV;
unsigned long clocks_flags;
if (unlikely(!clk_good(clk)))
goto out;
if (!clk->ops->set_parent)
goto out;
spin_lock_irqsave(&clocks_lock, clocks_flags);
ret = clk->ops->set_parent(clk, parent);
if (!ret) {
/* disable if usage count is 0 */
local_clk_disable(parent);
parent->usage += clk->usage;
clk->parent->usage -= clk->usage;
/* disable if new usage count is 0 */
local_clk_disable(clk->parent);
clk->parent = parent;
}
spin_unlock_irqrestore(&clocks_lock, clocks_flags);
out:
return ret;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
if (unlikely(!clk_good(clk)))
return NULL;
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
static int __init clk_init(void)
{
struct clk_lookup *cl;
struct clk_ops *ops;
spin_lock_init(&clocks_lock);
for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
cl++) {
if (cl->clk->flags & ENABLED)
clk_enable(cl->clk);
else
local_clk_disable(cl->clk);
ops = cl->clk->ops;
if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
ops && ops->set_rate)
ops->set_rate(cl->clk, cl->clk->rate);
if (cl->clk->flags & FIXED_RATE) {
if (cl->clk->flags & RATE_PROPAGATES)
propagate_rate(cl->clk);
} else {
if (ops && ops->get_rate)
ops->get_rate(cl->clk);
}
if (cl->clk->flags & NEEDS_SET_PARENT) {
if (ops && ops->set_parent)
ops->set_parent(cl->clk, cl->clk->parent);
}
}
clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
return 0;
}
arch_initcall(clk_init);
arch/arm/plat-stmp3xxx/clock.h deleted 100644 → 0
View file @ e8765afe
/*
* Clock control driver for Freescale STMP37XX/STMP378X - internal header file
*
* Author: Vitaly Wool <vital@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
#define __ARCH_ARM_STMX3XXX_CLOCK_H__
#ifndef __ASSEMBLER__
struct clk_ops {
int (*enable) (struct clk *);
int (*disable) (struct clk *);
long (*get_rate) (struct clk *);
long (*round_rate) (struct clk *, u32);
int (*set_rate) (struct clk *, u32);
int (*set_parent) (struct clk *, struct clk *);
};
struct clk {
struct clk *parent;
u32 rate;
u32 flags;
u8 scale_shift;
u8 enable_shift;
u8 bypass_shift;
u8 busy_bit;
s8 usage;
int enable_wait;
int enable_negate;
u32 saved_div;
void __iomem *enable_reg;
void __iomem *scale_reg;
void __iomem *bypass_reg;
void __iomem *busy_reg;
struct clk_ops *ops;
};
#endif /* __ASSEMBLER__ */
/* Flags */
#define RATE_PROPAGATES (1<<0)
#define NEEDS_INITIALIZATION (1<<1)
#define PARENT_SET_RATE (1<<2)
#define FIXED_RATE (1<<3)
#define ENABLED (1<<4)
#define NEEDS_SET_PARENT (1<<5)
#endif
arch/arm/plat-stmp3xxx/core.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X core routines
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/dma.h>
#include <mach/regs-clkctrl.h>
static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
{
u32 c;
int timeout;
/* the process of software reset of IP block is done
in several steps:
- clear SFTRST and wait for block is enabled;
- clear clock gating (CLKGATE bit);
- set the SFTRST again and wait for block is in reset;
- clear SFTRST and wait for reset completion.
*/
c = __raw_readl(hwreg);
c &= ~(1<<31); /* clear SFTRST */
__raw_writel(c, hwreg);
for (timeout = 1000000; timeout > 0; timeout--)
/* still in SFTRST state ? */
if ((__raw_readl(hwreg) & (1<<31)) == 0)
break;
if (timeout <= 0) {
printk(KERN_ERR"%s(%p): timeout when enabling\n",
__func__, hwreg);
return -ETIME;
}
c = __raw_readl(hwreg);
c &= ~(1<<30); /* clear CLKGATE */
__raw_writel(c, hwreg);
if (!just_enable) {
c = __raw_readl(hwreg);
c |= (1<<31); /* now again set SFTRST */
__raw_writel(c, hwreg);
for (timeout = 1000000; timeout > 0; timeout--)
/* poll until CLKGATE set */
if (__raw_readl(hwreg) & (1<<30))
break;
if (timeout <= 0) {
printk(KERN_ERR"%s(%p): timeout when resetting\n",
__func__, hwreg);
return -ETIME;
}
c = __raw_readl(hwreg);
c &= ~(1<<31); /* clear SFTRST */
__raw_writel(c, hwreg);
for (timeout = 1000000; timeout > 0; timeout--)
/* still in SFTRST state ? */
if ((__raw_readl(hwreg) & (1<<31)) == 0)
break;
if (timeout <= 0) {
printk(KERN_ERR"%s(%p): timeout when enabling "
"after reset\n", __func__, hwreg);
return -ETIME;
}
c = __raw_readl(hwreg);
c &= ~(1<<30); /* clear CLKGATE */
__raw_writel(c, hwreg);
}
for (timeout = 1000000; timeout > 0; timeout--)
/* still in SFTRST state ? */
if ((__raw_readl(hwreg) & (1<<30)) == 0)
break;
if (timeout <= 0) {
printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
__func__, hwreg);
return -ETIME;
}
return 0;
}
int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
{
int try = 10;
int r;
while (try--) {
r = __stmp3xxx_reset_block(hwreg, just_enable);
if (!r)
break;
pr_debug("%s: try %d failed\n", __func__, 10 - try);
}
return r;
}
EXPORT_SYMBOL(stmp3xxx_reset_block);
struct platform_device stmp3xxx_dbguart = {
.name = "stmp3xxx-dbguart",
.id = -1,
};
void __init stmp3xxx_init(void)
{
/* Turn off auto-slow and other tricks */
stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
stmp3xxx_dma_init();
}
arch/arm/plat-stmp3xxx/devices.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X platform devices
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <mach/dma.h>
#include <mach/platform.h>
#include <mach/stmp3xxx.h>
#include <mach/regs-lcdif.h>
#include <mach/regs-uartapp.h>
#include <mach/regs-gpmi.h>
#include <mach/regs-usbctrl.h>
#include <mach/regs-ssp.h>
#include <mach/regs-rtc.h>
static u64 common_dmamask = DMA_BIT_MASK(32);
static struct resource appuart_resources[] = {
{
.start = IRQ_UARTAPP_INTERNAL,
.end = IRQ_UARTAPP_INTERNAL,
.flags = IORESOURCE_IRQ,
}, {
.start = IRQ_UARTAPP_RX_DMA,
.end = IRQ_UARTAPP_RX_DMA,
.flags = IORESOURCE_IRQ,
}, {
.start = IRQ_UARTAPP_TX_DMA,
.end = IRQ_UARTAPP_TX_DMA,
.flags = IORESOURCE_IRQ,
}, {
.start = REGS_UARTAPP1_PHYS,
.end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
.flags = IORESOURCE_MEM,
}, {
/* Rx DMA channel */
.start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
.end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
.flags = IORESOURCE_DMA,
}, {
/* Tx DMA channel */
.start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
.end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
.flags = IORESOURCE_DMA,
},
};
struct platform_device stmp3xxx_appuart = {
.name = "stmp3xxx-appuart",
.id = 0,
.resource = appuart_resources,
.num_resources = ARRAY_SIZE(appuart_resources),
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device stmp3xxx_watchdog = {
.name = "stmp3xxx_wdt",
.id = -1,
};
static struct resource ts_resource[] = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_TOUCH_DETECT,
.end = IRQ_TOUCH_DETECT,
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_LRADC_CH5,
.end = IRQ_LRADC_CH5,
},
};
struct platform_device stmp3xxx_touchscreen = {
.name = "stmp3xxx_ts",
.id = -1,
.resource = ts_resource,
.num_resources = ARRAY_SIZE(ts_resource),
};
/*
* Keypad device
*/
struct platform_device stmp3xxx_keyboard = {
.name = "stmp3xxx-keyboard",
.id = -1,
};
static struct resource gpmi_resources[] = {
{
.flags = IORESOURCE_MEM,
.start = REGS_GPMI_PHYS,
.end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_GPMI_DMA,
.end = IRQ_GPMI_DMA,
}, {
.flags = IORESOURCE_DMA,
.start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
.end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
},
};
struct platform_device stmp3xxx_gpmi = {
.name = "gpmi",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = gpmi_resources,
.num_resources = ARRAY_SIZE(gpmi_resources),
};
static struct resource mmc1_resource[] = {
{
.flags = IORESOURCE_MEM,
.start = REGS_SSP1_PHYS,
.end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
}, {
.flags = IORESOURCE_DMA,
.start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
.end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_SSP1_DMA,
.end = IRQ_SSP1_DMA,
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_SSP_ERROR,
.end = IRQ_SSP_ERROR,
},
};
struct platform_device stmp3xxx_mmc = {
.name = "stmp3xxx-mmc",
.id = 1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = mmc1_resource,
.num_resources = ARRAY_SIZE(mmc1_resource),
};
static struct resource usb_resources[] = {
{
.start = REGS_USBCTRL_PHYS,
.end = REGS_USBCTRL_PHYS + SZ_4K,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_USB_CTRL,
.end = IRQ_USB_CTRL,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device stmp3xxx_udc = {
.name = "fsl-usb2-udc",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = usb_resources,
.num_resources = ARRAY_SIZE(usb_resources),
};
struct platform_device stmp3xxx_ehci = {
.name = "fsl-ehci",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = usb_resources,
.num_resources = ARRAY_SIZE(usb_resources),
};
static struct resource rtc_resources[] = {
{
.start = REGS_RTC_PHYS,
.end = REGS_RTC_PHYS + REGS_RTC_SIZE,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_RTC_ALARM,
.end = IRQ_RTC_ALARM,
.flags = IORESOURCE_IRQ,
}, {
.start = IRQ_RTC_1MSEC,
.end = IRQ_RTC_1MSEC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device stmp3xxx_rtc = {
.name = "stmp3xxx-rtc",
.id = -1,
.resource = rtc_resources,
.num_resources = ARRAY_SIZE(rtc_resources),
};
static struct resource ssp1_resources[] = {
{
.start = REGS_SSP1_PHYS,
.end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_SSP1_DMA,
.end = IRQ_SSP1_DMA,
.flags = IORESOURCE_IRQ,
}, {
.start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
.end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
.flags = IORESOURCE_DMA,
},
};
static struct resource ssp2_resources[] = {
{
.start = REGS_SSP2_PHYS,
.end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_SSP2_DMA,
.end = IRQ_SSP2_DMA,
.flags = IORESOURCE_IRQ,
}, {
.start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
.end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
.flags = IORESOURCE_DMA,
},
};
struct platform_device stmp3xxx_spi1 = {
.name = "stmp3xxx_ssp",
.id = 1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = ssp1_resources,
.num_resources = ARRAY_SIZE(ssp1_resources),
};
struct platform_device stmp3xxx_spi2 = {
.name = "stmp3xxx_ssp",
.id = 2,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = ssp2_resources,
.num_resources = ARRAY_SIZE(ssp2_resources),
};
static struct resource fb_resource[] = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_LCDIF_DMA,
.end = IRQ_LCDIF_DMA,
}, {
.flags = IORESOURCE_IRQ,
.start = IRQ_LCDIF_ERROR,
.end = IRQ_LCDIF_ERROR,
}, {
.flags = IORESOURCE_MEM,
.start = REGS_LCDIF_PHYS,
.end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
},
};
struct platform_device stmp3xxx_framebuffer = {
.name = "stmp3xxx-fb",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(fb_resource),
.resource = fb_resource,
};
#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
static char *cmdline_device_##name; \
static int cmdline_device_##name##_setup(char *dev) \
{ \
cmdline_device_##name = dev + 1; \
return 0; \
} \
__setup(#name, cmdline_device_##name##_setup); \
int stmp3xxx_##name##_device_register(void) \
{ \
struct platform_device *d = NULL; \
if (!cmdline_device_##name || \
!strcmp(cmdline_device_##name, #dev1)) \
d = &stmp3xxx_##dev1; \
else if (!strcmp(cmdline_device_##name, #dev2)) \
d = &stmp3xxx_##dev2; \
else \
printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
#name, cmdline_device_##name); \
return d ? platform_device_register(d) : -ENOENT; \
}
CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
struct platform_device stmp3xxx_backlight = {
.name = "stmp3xxx-bl",
.id = -1,
};
struct platform_device stmp3xxx_rotdec = {
.name = "stmp3xxx-rotdec",
.id = -1,
};
struct platform_device stmp3xxx_persistent = {
.name = "stmp3xxx-persistent",
.id = -1,
};
struct platform_device stmp3xxx_dcp_bootstream = {
.name = "stmp3xxx-dcpboot",
.id = -1,
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource dcp_resources[] = {
{
.start = IRQ_DCP_VMI,
.end = IRQ_DCP_VMI,
.flags = IORESOURCE_IRQ,
}, {
.start = IRQ_DCP,
.end = IRQ_DCP,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device stmp3xxx_dcp = {
.name = "stmp3xxx-dcp",
.id = -1,
.resource = dcp_resources,
.num_resources = ARRAY_SIZE(dcp_resources),
.dev = {
.dma_mask = &common_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource battery_resource[] = {
{
.flags = IORESOURCE_IRQ,
.start = IRQ_VDD5V,
.end = IRQ_VDD5V,
},
};
struct platform_device stmp3xxx_battery = {
.name = "stmp3xxx-battery",
.resource = battery_resource,
.num_resources = ARRAY_SIZE(battery_resource),
};
arch/arm/plat-stmp3xxx/dma.c deleted 100644 → 0
View file @ e8765afe
/*
* DMA helper routines for Freescale STMP37XX/STMP378X
*
* Author: dmitry pervushin <dpervushin@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/sysdev.h>
#include <linux/cpufreq.h>
#include <asm/page.h>
#include <mach/platform.h>
#include <mach/dma.h>
#include <mach/regs-apbx.h>
#include <mach/regs-apbh.h>
static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
static const size_t pool_alignment = 8;
static struct stmp3xxx_dma_user {
void *pool;
int inuse;
const char *name;
} channels[MAX_DMA_CHANNELS];
#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
#define IS_USED(ch) (channels[ch].inuse)
int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
{
struct stmp3xxx_dma_user *user;
int err = 0;
user = channels + ch;
if (!IS_VALID_CHANNEL(ch)) {
err = -ENODEV;
goto out;
}
if (IS_USED(ch)) {
err = -EBUSY;
goto out;
}
/* Create a pool to allocate dma commands from */
user->pool = dma_pool_create(name, dev, pool_item_size,
pool_alignment, PAGE_SIZE);
if (user->pool == NULL) {
err = -ENOMEM;
goto out;
}
user->name = name;
user->inuse++;
out:
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_request);
int stmp3xxx_dma_release(int ch)
{
struct stmp3xxx_dma_user *user = channels + ch;
int err = 0;
if (!IS_VALID_CHANNEL(ch)) {
err = -ENODEV;
goto out;
}
if (!IS_USED(ch)) {
err = -EBUSY;
goto out;
}
BUG_ON(user->pool == NULL);
dma_pool_destroy(user->pool);
user->inuse--;
out:
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_release);
int stmp3xxx_dma_read_semaphore(int channel)
{
int sem = -1;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
sem &= BM_APBH_CHn_SEMA_PHORE;
sem >>= BP_APBH_CHn_SEMA_PHORE;
break;
case STMP3XXX_BUS_APBX:
sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
STMP3XXX_DMA_CHANNEL(channel) * 0x70);
sem &= BM_APBX_CHn_SEMA_PHORE;
sem >>= BP_APBX_CHn_SEMA_PHORE;
break;
default:
BUG();
}
return sem;
}
EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
int stmp3xxx_dma_allocate_command(int channel,
struct stmp3xxx_dma_descriptor *descriptor)
{
struct stmp3xxx_dma_user *user = channels + channel;
int err = 0;
if (!IS_VALID_CHANNEL(channel)) {
err = -ENODEV;
goto out;
}
if (!IS_USED(channel)) {
err = -EBUSY;
goto out;
}
if (descriptor == NULL) {
err = -EINVAL;
goto out;
}
/* Allocate memory for a command from the buffer */
descriptor->command =
dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
/* Check it worked */
if (!descriptor->command) {
err = -ENOMEM;
goto out;
}
memset(descriptor->command, 0, pool_item_size);
out:
WARN_ON(err);
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
int stmp3xxx_dma_free_command(int channel,
struct stmp3xxx_dma_descriptor *descriptor)
{
int err = 0;
if (!IS_VALID_CHANNEL(channel)) {
err = -ENODEV;
goto out;
}
if (!IS_USED(channel)) {
err = -EBUSY;
goto out;
}
/* Return the command memory to the pool */
dma_pool_free(channels[channel].pool, descriptor->command,
descriptor->handle);
/* Initialise descriptor so we're not tempted to use it */
descriptor->command = NULL;
descriptor->handle = 0;
descriptor->virtual_buf_ptr = NULL;
descriptor->next_descr = NULL;
WARN_ON(err);
out:
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_free_command);
void stmp3xxx_dma_go(int channel,
struct stmp3xxx_dma_descriptor *head, u32 semaphore)
{
int ch = STMP3XXX_DMA_CHANNEL(channel);
void __iomem *c, *s;
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
break;
case STMP3XXX_BUS_APBX:
c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
break;
default:
return;
}
/* Set next command */
__raw_writel(head->handle, c);
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
__raw_writel(semaphore, s);
}
EXPORT_SYMBOL(stmp3xxx_dma_go);
int stmp3xxx_dma_running(int channel)
{
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
BM_APBH_CHn_SEMA_PHORE;
case STMP3XXX_BUS_APBX:
return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
BM_APBX_CHn_SEMA_PHORE;
default:
BUG();
return 0;
}
}
EXPORT_SYMBOL(stmp3xxx_dma_running);
/*
* Circular dma chain management
*/
void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
{
int i;
for (i = 0; i < chain->total_count; i++)
stmp3xxx_dma_free_command(
STMP3XXX_DMA(chain->channel, chain->bus),
&chain->chain[i]);
}
EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
struct stmp3xxx_dma_descriptor descriptors[],
unsigned items)
{
int i;
int err = 0;
if (items == 0)
return err;
for (i = 0; i < items; i++) {
err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
if (err) {
WARN_ON(err);
/*
* Couldn't allocate the whole chain.
* deallocate what has been allocated
*/
if (i) {
do {
stmp3xxx_dma_free_command(ch,
&descriptors
[i]);
} while (i-- > 0);
}
return err;
}
/* link them! */
if (i > 0) {
descriptors[i - 1].next_descr = &descriptors[i];
descriptors[i - 1].command->next =
descriptors[i].handle;
}
}
/* make list circular */
descriptors[items - 1].next_descr = &descriptors[0];
descriptors[items - 1].command->next = descriptors[0].handle;
chain->total_count = items;
chain->chain = descriptors;
chain->free_index = 0;
chain->active_index = 0;
chain->cooked_index = 0;
chain->free_count = items;
chain->active_count = 0;
chain->cooked_count = 0;
chain->bus = STMP3XXX_DMA_BUS(ch);
chain->channel = STMP3XXX_DMA_CHANNEL(ch);
return err;
}
EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
{
BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
chain->free_index = 0;
chain->active_index = 0;
chain->cooked_index = 0;
chain->free_count = chain->total_count;
chain->active_count = 0;
chain->cooked_count = 0;
}
EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
unsigned count)
{
BUG_ON(chain->cooked_count < count);
chain->cooked_count -= count;
chain->cooked_index += count;
chain->cooked_index %= chain->total_count;
chain->free_count += count;
}
EXPORT_SYMBOL(stmp37xx_circ_advance_free);
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
unsigned count)
{
void __iomem *c;
u32 mask_clr, mask;
BUG_ON(chain->free_count < count);
chain->free_count -= count;
chain->free_index += count;
chain->free_index %= chain->total_count;
chain->active_count += count;
switch (chain->bus) {
case STMP3XXX_BUS_APBH:
c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
break;
case STMP3XXX_BUS_APBX:
c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
break;
default:
BUG();
return;
}
/* Set counting semaphore (kicks off transfer). Assumes
peripheral has been set up correctly */
stmp3xxx_clearl(mask_clr, c);
stmp3xxx_setl(mask, c);
}
EXPORT_SYMBOL(stmp37xx_circ_advance_active);
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
{
unsigned cooked;
cooked = chain->active_count -
stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
chain->active_count -= cooked;
chain->active_index += cooked;
chain->active_index %= chain->total_count;
chain->cooked_count += cooked;
return cooked;
}
EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
void stmp3xxx_dma_set_alt_target(int channel, int function)
{
#if defined(CONFIG_ARCH_STMP37XX)
unsigned bits = 4;
#elif defined(CONFIG_ARCH_STMP378X)
unsigned bits = 2;
#else
#error wrong arch
#endif
int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
unsigned mask = (1<<bits) - 1;
void __iomem *c;
BUG_ON(function < 0 || function >= (1<<bits));
pr_debug("%s: channel = %d, using mask %x, "
"shift = %d\n", __func__, channel, mask, shift);
switch (STMP3XXX_DMA_BUS(channel)) {
case STMP3XXX_BUS_APBH:
c = REGS_APBH_BASE + HW_APBH_DEVSEL;
break;
case STMP3XXX_BUS_APBX:
c = REGS_APBX_BASE + HW_APBX_DEVSEL;
break;
default:
BUG();
}
stmp3xxx_clearl(mask << shift, c);
stmp3xxx_setl(mask << shift, c);
}
EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
void stmp3xxx_dma_suspend(void)
{
stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
}
void stmp3xxx_dma_resume(void)
{
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
REGS_APBX_BASE + HW_APBX_CTRL0);
}
#ifdef CONFIG_CPU_FREQ
struct dma_notifier_block {
struct notifier_block nb;
void *data;
};
static int dma_cpufreq_notifier(struct notifier_block *self,
unsigned long phase, void *p)
{
switch (phase) {
case CPUFREQ_POSTCHANGE:
stmp3xxx_dma_resume();
break;
case CPUFREQ_PRECHANGE:
stmp3xxx_dma_suspend();
break;
default:
break;
}
return NOTIFY_DONE;
}
static struct dma_notifier_block dma_cpufreq_nb = {
.nb = {
.notifier_call = dma_cpufreq_notifier,
},
};
#endif /* CONFIG_CPU_FREQ */
void __init stmp3xxx_dma_init(void)
{
stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
REGS_APBH_BASE + HW_APBH_CTRL0);
stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
REGS_APBX_BASE + HW_APBX_CTRL0);
#ifdef CONFIG_CPU_FREQ
cpufreq_register_notifier(&dma_cpufreq_nb.nb,
CPUFREQ_TRANSITION_NOTIFIER);
#endif /* CONFIG_CPU_FREQ */
}
arch/arm/plat-stmp3xxx/include/mach/clkdev.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
arch/arm/plat-stmp3xxx/include/mach/cputype.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X CPU type detection
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_CPU_H
#define __ASM_PLAT_CPU_H
#ifdef CONFIG_ARCH_STMP37XX
#define cpu_is_stmp37xx() (1)
#else
#define cpu_is_stmp37xx() (0)
#endif
#ifdef CONFIG_ARCH_STMP378X
#define cpu_is_stmp378x() (1)
#else
#define cpu_is_stmp378x() (0)
#endif
#endif /* __ASM_PLAT_CPU_H */
arch/arm/plat-stmp3xxx/include/mach/debug-macro.S deleted 100644 → 0
View file @ e8765afe
/*
* Debugging macro include header
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
.macro addruart, rp, rv
mov \rp, #0x00070000
add \rv, \rp, #0xf0000000 @ virtual base
add \rp, \rp, #0x80000000 @ physical base
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #0] @ data register at 0
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
arch/arm/plat-stmp3xxx/include/mach/dma.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X DMA helper interface
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_DMA_H
#define __ASM_PLAT_STMP3XXX_DMA_H
#include <linux/platform_device.h>
#include <linux/dmapool.h>
#if !defined(MAX_PIO_WORDS)
#define MAX_PIO_WORDS (15)
#endif
#define STMP3XXX_BUS_APBH 0
#define STMP3XXX_BUS_APBX 1
#define STMP3XXX_DMA_MAX_CHANNEL 16
#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 32
struct stmp3xxx_dma_command {
u32 next;
u32 cmd;
union {
u32 buf_ptr;
u32 alternate;
};
u32 pio_words[MAX_PIO_WORDS];
};
struct stmp3xxx_dma_descriptor {
struct stmp3xxx_dma_command *command;
dma_addr_t handle;
/* The virtual address of the buffer pointer */
void *virtual_buf_ptr;
/* The next descriptor in a the DMA chain (optional) */
struct stmp3xxx_dma_descriptor *next_descr;
};
struct stmp37xx_circ_dma_chain {
unsigned total_count;
struct stmp3xxx_dma_descriptor *chain;
unsigned free_index;
unsigned free_count;
unsigned active_index;
unsigned active_count;
unsigned cooked_index;
unsigned cooked_count;
int bus;
unsigned channel;
};
static inline struct stmp3xxx_dma_descriptor
*stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
{
return &(chain->chain[chain->free_index]);
}
static inline struct stmp3xxx_dma_descriptor
*stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
{
return &(chain->chain[chain->cooked_index]);
}
int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
int stmp3xxx_dma_release(int ch);
int stmp3xxx_dma_allocate_command(int ch,
struct stmp3xxx_dma_descriptor *descriptor);
int stmp3xxx_dma_free_command(int ch,
struct stmp3xxx_dma_descriptor *descriptor);
void stmp3xxx_dma_continue(int channel, u32 semaphore);
void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
u32 semaphore);
int stmp3xxx_dma_running(int ch);
int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
struct stmp3xxx_dma_descriptor descriptors[],
unsigned items);
void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
unsigned count);
void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
unsigned count);
unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
int stmp3xxx_dma_read_semaphore(int ch);
void stmp3xxx_dma_init(void);
void stmp3xxx_dma_set_alt_target(int ch, int target);
void stmp3xxx_dma_suspend(void);
void stmp3xxx_dma_resume(void);
/*
* STMP37xx and STMP378x have different DMA control
* registers layout
*/
void stmp3xxx_arch_dma_freeze(int ch);
void stmp3xxx_arch_dma_unfreeze(int ch);
void stmp3xxx_arch_dma_reset_channel(int ch);
void stmp3xxx_arch_dma_enable_interrupt(int ch);
void stmp3xxx_arch_dma_clear_interrupt(int ch);
int stmp3xxx_arch_dma_is_interrupt(int ch);
static inline void stmp3xxx_dma_reset_channel(int ch)
{
stmp3xxx_arch_dma_reset_channel(ch);
}
static inline void stmp3xxx_dma_freeze(int ch)
{
stmp3xxx_arch_dma_freeze(ch);
}
static inline void stmp3xxx_dma_unfreeze(int ch)
{
stmp3xxx_arch_dma_unfreeze(ch);
}
static inline void stmp3xxx_dma_enable_interrupt(int ch)
{
stmp3xxx_arch_dma_enable_interrupt(ch);
}
static inline void stmp3xxx_dma_clear_interrupt(int ch)
{
stmp3xxx_arch_dma_clear_interrupt(ch);
}
static inline int stmp3xxx_dma_is_interrupt(int ch)
{
return stmp3xxx_arch_dma_is_interrupt(ch);
}
#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
arch/arm/plat-stmp3xxx/include/mach/gpio.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X GPIO interface
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_GPIO_H
#define __ASM_PLAT_GPIO_H
#define ARCH_NR_GPIOS (32 * 3)
#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
#define gpio_get_value(gpio) __gpio_get_value(gpio)
#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
#include <asm-generic/gpio.h>
#endif /* __ASM_PLAT_GPIO_H */
arch/arm/plat-stmp3xxx/include/mach/gpmi.h deleted 100644 → 0
View file @ e8765afe
#ifndef __MACH_GPMI_H
#include <linux/mtd/partitions.h>
#include <mach/regs-gpmi.h>
struct gpmi_platform_data {
void *pins;
int nr_parts;
struct mtd_partition *parts;
const char *part_types[];
};
#endif
arch/arm/plat-stmp3xxx/include/mach/hardware.h deleted 100644 → 0
View file @ e8765afe
/*
* This file contains the hardware definitions of the Freescale STMP3XXX
*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
#define IO_BASE 0xF0000000 /* VA of IO */
#define IO_SIZE 0x00100000 /* How much? */
#define IO_START 0x80000000 /* PA of IO */
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
#endif
arch/arm/plat-stmp3xxx/include/mach/io.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
arch/arm/plat-stmp3xxx/include/mach/memory.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PLAT_PHYS_OFFSET UL(0x40000000)
#endif
arch/arm/plat-stmp3xxx/include/mach/mmc.h deleted 100644 → 0
View file @ e8765afe
#ifndef _MACH_MMC_H
#define _MACH_MMC_H
#include <mach/regs-ssp.h>
struct stmp3xxxmmc_platform_data {
int (*get_wp)(void);
unsigned long (*setclock)(void __iomem *base, unsigned long);
void (*cmd_pullup)(int);
int (*hw_init)(void);
void (*hw_release)(void);
};
#endif
arch/arm/plat-stmp3xxx/include/mach/pinmux.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X Pin Multiplexing
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __PINMUX_H
#define __PINMUX_H
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <asm-generic/gpio.h>
/* Pin definitions */
#include "pins.h"
#include <mach/pins.h>
/*
* Each pin may be routed up to four different HW interfaces
* including GPIO
*/
enum pin_fun {
PIN_FUN1 = 0,
PIN_FUN2,
PIN_FUN3,
PIN_GPIO,
};
/*
* Each pin may have different output drive strength in range from
* 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
*/
enum pin_strength {
PIN_4MA = 0,
PIN_8MA,
PIN_12MA,
PIN_16MA,
PIN_20MA,
};
/*
* Each pin can be programmed for 1.8V or 3.3V
*/
enum pin_voltage {
PIN_1_8V = 0,
PIN_3_3V,
};
/*
* Structure to define a group of pins and their parameters
*/
struct pin_desc {
unsigned id;
enum pin_fun fun;
enum pin_strength strength;
enum pin_voltage voltage;
unsigned pullup:1;
};
struct pin_group {
struct pin_desc *pins;
int nr_pins;
};
/* Set pin drive strength */
void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
const char *label);
/* Set pin voltage */
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
const char *label);
/* Enable pull-up resistor for a pin */
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
/*
* Request a pin ownership, only one module (identified by @label)
* may own a pin.
*/
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
/* Release pin */
void stmp3xxx_release_pin(unsigned id, const char *label);
void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
/*
* Each bank is associated with a number of registers to control
* pin function, drive strength, voltage and pull-up reigster. The
* number of registers of a given type depends on the number of bits
* describin particular pin.
*/
#define HW_MUXSEL_NUM 2 /* registers per bank */
#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
#define HW_DRIVE_NUM 4 /* registers per bank */
#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
#define HW_DRIVE_PIN_NUM 8 /* pins per register */
#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
struct stmp3xxx_pinmux_bank {
struct gpio_chip chip;
/* Pins allocation map */
unsigned long pin_map;
/* Pin owner names */
const char *pin_labels[32];
/* Bank registers */
void __iomem *hw_muxsel[HW_MUXSEL_NUM];
void __iomem *hw_drive[HW_DRIVE_NUM];
void __iomem *hw_pull;
void __iomem *pin2irq,
*irqlevel,
*irqpolarity,
*irqen,
*irqstat;
/* HW MUXSEL register function bit values */
u8 functions[HW_MUXSEL_PINFUN_NUM];
/*
* HW DRIVE register strength bit values:
* 0xff - requested strength is not supported for this bank
*/
u8 strengths[HW_DRIVE_PINDRV_NUM];
/* GPIO things */
void __iomem *hw_gpio_in,
*hw_gpio_out,
*hw_gpio_doe;
int irq, virq;
};
int __init stmp3xxx_pinmux_init(int virtual_irq_start);
#endif /* __PINMUX_H */
arch/arm/plat-stmp3xxx/include/mach/pins.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_PINS_H
#define __ASM_PLAT_PINS_H
#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
/*
* Special invalid pin identificator to show a pin doesn't exist
*/
#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
#endif /* __ASM_PLAT_PINS_H */
arch/arm/plat-stmp3xxx/include/mach/platform.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_PLATFORM_H
#define __ASM_PLAT_PLATFORM_H
#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif
#include <asm/sizes.h>
/* Virtual address where registers are mapped */
#define STMP3XXX_REGS_PHBASE 0x80000000
#ifdef __ASSEMBLER__
#define STMP3XXX_REGS_BASE 0xF0000000
#else
#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
#endif
#define STMP3XXX_REGS_SIZE SZ_1M
/* Virtual address where OCRAM is mapped */
#define STMP3XXX_OCRAM_PHBASE 0x00000000
#ifdef __ASSEMBLER__
#define STMP3XXX_OCRAM_BASE 0xf1000000
#else
#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
#endif
#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
#ifdef CONFIG_ARCH_STMP37XX
#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
#endif
#ifdef CONFIG_ARCH_STMP378X
#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
#endif
#define HW_STMP3XXX_SET 0x04
#define HW_STMP3XXX_CLR 0x08
#define HW_STMP3XXX_TOG 0x0c
#ifndef __ASSEMBLER__
static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
{
__raw_writel(v, r + HW_STMP3XXX_CLR);
}
static inline void stmp3xxx_setl(u32 v, void __iomem *r)
{
__raw_writel(v, r + HW_STMP3XXX_SET);
}
#endif
#define BF(value, field) (((value) << BP_##field) & BM_##field)
#endif /* __ASM_ARCH_PLATFORM_H */
arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X core structure and function declarations
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_STMP3XXX_H
#define __ASM_PLAT_STMP3XXX_H
#include <linux/irq.h>
extern struct sys_timer stmp3xxx_timer;
void stmp3xxx_init_irq(struct irq_chip *chip);
void stmp3xxx_init(void);
int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
extern struct platform_device stmp3xxx_dbguart,
stmp3xxx_appuart,
stmp3xxx_watchdog,
stmp3xxx_touchscreen,
stmp3xxx_keyboard,
stmp3xxx_gpmi,
stmp3xxx_mmc,
stmp3xxx_udc,
stmp3xxx_ehci,
stmp3xxx_rtc,
stmp3xxx_spi1,
stmp3xxx_spi2,
stmp3xxx_backlight,
stmp3xxx_rotdec,
stmp3xxx_dcp,
stmp3xxx_dcp_bootstream,
stmp3xxx_persistent,
stmp3xxx_framebuffer,
stmp3xxx_battery;
int stmp3xxx_ssp1_device_register(void);
int stmp3xxx_ssp2_device_register(void);
struct pin_group;
void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
#endif /* __ASM_PLAT_STMP3XXX_H */
arch/arm/plat-stmp3xxx/include/mach/system.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright (C) 2005 Sigmatel Inc
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/proc-fns.h>
#include <mach/platform.h>
#include <mach/regs-clkctrl.h>
#include <mach/regs-power.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
/* Set BATTCHRG to default value */
__raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
/* Set MINPWR to default value */
__raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
/* Reset digital side of chip (but not power or RTC) */
__raw_writel(BM_CLKCTRL_RESET_DIG,
REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
/* Should not return */
}
#endif
arch/arm/plat-stmp3xxx/include/mach/timex.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright (C) 1999 ARM Limited
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* System time clock is sourced from the 32k clock
*/
#define CLOCK_TICK_RATE (32768)
arch/arm/plat-stmp3xxx/include/mach/uncompress.h deleted 100644 → 0
View file @ e8765afe
/*
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __ASM_PLAT_UNCOMPRESS_H
#define __ASM_PLAT_UNCOMPRESS_H
/*
* Register includes are for when the MMU enabled; we need to define our
* own stuff here for pre-MMU use
*/
#define UARTDBG_BASE 0x80070000
#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
/*
* This does not append a newline
*/
static void putc(char c)
{
/* Wait for TX fifo empty */
while ((UART(6) & (1<<7)) == 0)
continue;
/* Write byte */
UART(0) = c;
/* Wait for last bit to exit the UART */
while (UART(6) & (1<<3))
continue;
}
static void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif /* __ASM_PLAT_UNCOMPRESS_H */
arch/arm/plat-stmp3xxx/include/mach/vmalloc.h deleted 100644 → 0
View file @ e8765afe
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define VMALLOC_END 0xf0000000UL
arch/arm/plat-stmp3xxx/irq.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP37XX/STMP378X common interrupt handling code
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/sysdev.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/regs-icoll.h>
void __init stmp3xxx_init_irq(struct irq_chip *chip)
{
unsigned int i, lv;
/* Reset the interrupt controller */
stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
/* Disable all interrupts initially */
for (i = 0; i < NR_REAL_IRQS; i++) {
chip->irq_mask(irq_get_irq_data(i));
irq_set_chip_and_handler(i, chip, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
/* Ensure vector is cleared */
for (lv = 0; lv < 4; lv++)
__raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
__raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
/* Barrier */
(void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
}
arch/arm/plat-stmp3xxx/pinmux.c deleted 100644 → 0
View file @ e8765afe
/*
* Freescale STMP378X/STMP378X Pin Multiplexing
*
* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#define DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/sysdev.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <mach/regs-pinctrl.h>
#include <mach/pins.h>
#include <mach/pinmux.h>
#define NR_BANKS ARRAY_SIZE(pinmux_banks)
static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
[0] = {
.hw_muxsel = {
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
},
.hw_drive = {
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
},
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
.irq = IRQ_GPIO0,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
},
[1] = {
.hw_muxsel = {
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
},
.hw_drive = {
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
},
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
.irq = IRQ_GPIO1,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
},
[2] = {
.hw_muxsel = {
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
},
.hw_drive = {
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
},
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
.functions = { 0x0, 0x1, 0x2, 0x3 },
.strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
.irq = IRQ_GPIO2,
.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
},
[3] = {
.hw_muxsel = {
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
},
.hw_drive = {
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
NULL,
},
.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
.functions = {0x0, 0x1, 0x2, 0x3},
.strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
},
};
static inline struct stmp3xxx_pinmux_bank *
stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
{
unsigned b, p;
b = STMP3XXX_PINID_TO_BANK(id);
p = STMP3XXX_PINID_TO_PINNUM(id);
BUG_ON(b >= NR_BANKS);
if (bank)
*bank = b;
if (pin)
*pin = p;
return &pinmux_banks[b];
}
/* Check if requested pin is owned by caller */
static int stmp3xxx_check_pin(unsigned id, const char *label)
{
unsigned pin;
struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
if (!test_bit(pin, &pm->pin_map)) {
printk(KERN_WARNING
"%s: Accessing free pin %x, caller %s\n",
__func__, id, label);
return -EINVAL;
}
if (label && pm->pin_labels[pin] &&
strcmp(label, pm->pin_labels[pin])) {
printk(KERN_WARNING
"%s: Wrong pin owner %x, caller %s owner %s\n",
__func__, id, label, pm->pin_labels[pin]);
return -EINVAL;
}
return 0;
}
void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
const char *label)
{
struct stmp3xxx_pinmux_bank *pbank;
void __iomem *hwdrive;
u32 shift, val;
u32 bank, pin;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
bank, pin, strength);
hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
val = pbank->strengths[strength];
if (val == 0xff) {
printk(KERN_WARNING
"%s: strength is not supported for bank %d, caller %s",
__func__, bank, label);
return;
}
if (stmp3xxx_check_pin(id, label))
return;
pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
val << shift, hwdrive);
stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
stmp3xxx_setl(val << shift, hwdrive);
}
void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
const char *label)
{
struct stmp3xxx_pinmux_bank *pbank;
void __iomem *hwdrive;
u32 shift;
u32 bank, pin;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
bank, pin, voltage);
hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
if (stmp3xxx_check_pin(id, label))
return;
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
__func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
if (voltage == PIN_1_8V)
stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
else
stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
}
void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
{
struct stmp3xxx_pinmux_bank *pbank;
void __iomem *hwpull;
u32 bank, pin;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
bank, pin, enable);
hwpull = pbank->hw_pull;
if (stmp3xxx_check_pin(id, label))
return;
pr_debug("%s: changing 0x%x bit in 0x%p register\n",
__func__, 1 << pin, hwpull);
if (enable)
stmp3xxx_setl(1 << pin, hwpull);
else
stmp3xxx_clearl(1 << pin, hwpull);
}
int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
{
struct stmp3xxx_pinmux_bank *pbank;
u32 bank, pin;
int ret = 0;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
bank, pin, fun);
if (test_bit(pin, &pbank->pin_map)) {
printk(KERN_WARNING
"%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
__func__, bank, pin, label, pbank->pin_labels[pin]);
return -EBUSY;
}
set_bit(pin, &pbank->pin_map);
pbank->pin_labels[pin] = label;
stmp3xxx_set_pin_type(id, fun);
return ret;
}
void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
{
struct stmp3xxx_pinmux_bank *pbank;
void __iomem *hwmux;
u32 shift, val;
u32 bank, pin;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
val = pbank->functions[fun];
shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
pr_debug("%s: writing 0x%x to 0x%p register\n",
__func__, val << shift, hwmux);
stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
stmp3xxx_setl(val << shift, hwmux);
}
void stmp3xxx_release_pin(unsigned id, const char *label)
{
struct stmp3xxx_pinmux_bank *pbank;
u32 bank, pin;
pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
if (stmp3xxx_check_pin(id, label))
return;
clear_bit(pin, &pbank->pin_map);
pbank->pin_labels[pin] = NULL;
}
int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
{
struct pin_desc *pin;
int p;
int err = 0;
/* Allocate and configure pins */
for (p = 0; p < pin_group->nr_pins; p++) {
pr_debug("%s: #%d\n", __func__, p);
pin = &pin_group->pins[p];
err = stmp3xxx_request_pin(pin->id, pin->fun, label);
if (err)
goto out_err;
stmp3xxx_pin_strength(pin->id, pin->strength, label);
stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
}
return 0;
out_err:
/* Release allocated pins in case of error */
while (--p >= 0) {
pr_debug("%s: releasing #%d\n", __func__, p);
stmp3xxx_release_pin(pin_group->pins[p].id, label);
}
return err;
}
EXPORT_SYMBOL(stmp3xxx_request_pin_group);
void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
{
struct pin_desc *pin;
int p;
for (p = 0; p < pin_group->nr_pins; p++) {
pin = &pin_group->pins[p];
stmp3xxx_release_pin(pin->id, label);
}
}
EXPORT_SYMBOL(stmp3xxx_release_pin_group);
static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
{
struct stmp3xxx_pinmux_bank *pm;
for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
*bank = pm;
*gpio = d->irq - pm->virq;
return 0;
}
return -ENOENT;
}
static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
{
struct stmp3xxx_pinmux_bank *pm;
unsigned gpio;
int l, p;
stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
l = 0; p = 1; break;
case IRQ_TYPE_EDGE_FALLING:
l = 0; p = 0; break;
case IRQ_TYPE_LEVEL_HIGH:
l = 1; p = 1; break;
case IRQ_TYPE_LEVEL_LOW:
l = 1; p = 0; break;
default:
pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
__func__, type);
return -ENXIO;
}
if (l)
stmp3xxx_setl(1 << gpio, pm->irqlevel);
else
stmp3xxx_clearl(1 << gpio, pm->irqlevel);
if (p)
stmp3xxx_setl(1 << gpio, pm->irqpolarity);
else
stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
return 0;
}
static void stmp3xxx_pin_ack_irq(struct irq_data *d)
{
u32 stat;
struct stmp3xxx_pinmux_bank *pm;
unsigned gpio;
stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
stat = __raw_readl(pm->irqstat) & (1 << gpio);
stmp3xxx_clearl(stat, pm->irqstat);
}
static void stmp3xxx_pin_mask_irq(struct irq_data *d)
{
struct stmp3xxx_pinmux_bank *pm;
unsigned gpio;
stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
stmp3xxx_clearl(1 << gpio, pm->irqen);
stmp3xxx_clearl(1 << gpio, pm->pin2irq);
}
static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
{
struct stmp3xxx_pinmux_bank *pm;
unsigned gpio;
stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
stmp3xxx_setl(1 << gpio, pm->irqen);
stmp3xxx_setl(1 << gpio, pm->pin2irq);
}
static inline
struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
{
return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
}
static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
return pm->virq + offset;
}
static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
unsigned v;
v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
return v ? 1 : 0;
}
static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
if (v)
stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
else
stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
}
static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
stmp3xxx_gpio_set(chip, offset, v);
return 0;
}
static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
{
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
return 0;
}
static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
}
static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
{
stmp3xxx_release_pin(chip->base + offset, "gpio");
}
static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
{
struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
int gpio_irq = pm->virq;
u32 stat = __raw_readl(pm->irqstat);
while (stat) {
if (stat & 1)
generic_handle_irq(gpio_irq);
gpio_irq++;
stat >>= 1;
}
}
static struct irq_chip gpio_irq_chip = {
.irq_ack = stmp3xxx_pin_ack_irq,
.irq_mask = stmp3xxx_pin_mask_irq,
.irq_unmask = stmp3xxx_pin_unmask_irq,
.irq_set_type = stmp3xxx_set_irqtype,
};
int __init stmp3xxx_pinmux_init(int virtual_irq_start)
{
int b, r = 0;
struct stmp3xxx_pinmux_bank *pm;
int virq;
for (b = 0; b < 3; b++) {
/* only banks 0,1,2 are allowed to GPIO */
pm = pinmux_banks + b;
pm->chip.base = 32 * b;
pm->chip.ngpio = 32;
pm->chip.owner = THIS_MODULE;
pm->chip.can_sleep = 1;
pm->chip.exported = 1;
pm->chip.to_irq = stmp3xxx_gpio_to_irq;
pm->chip.direction_input = stmp3xxx_gpio_input;
pm->chip.direction_output = stmp3xxx_gpio_output;
pm->chip.get = stmp3xxx_gpio_get;
pm->chip.set = stmp3xxx_gpio_set;
pm->chip.request = stmp3xxx_gpio_request;
pm->chip.free = stmp3xxx_gpio_free;
pm->virq = virtual_irq_start + b * 32;
for (virq = pm->virq; virq < pm->virq; virq++) {
gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
irq_set_chip_and_handler(virq, &gpio_irq_chip,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
}
r = gpiochip_add(&pm->chip);
if (r < 0)
break;
irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
irq_set_handler_data(pm->irq, pm);
}
return r;
}
MODULE_AUTHOR("Vladislav Buzov");
MODULE_LICENSE("GPL");
arch/arm/plat-stmp3xxx/timer.c deleted 100644 → 0
View file @ e8765afe
/*
* System timer for Freescale STMP37XX/STMP378X
*
* Embedded Alley Solutions, Inc <source@embeddedalley.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*/
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <asm/mach/time.h>
#include <mach/stmp3xxx.h>
#include <mach/platform.h>
#include <mach/regs-timrot.h>
static irqreturn_t
stmp3xxx_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
/* timer 0 */
if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
BM_TIMROT_TIMCTRLn_IRQ) {
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
c->event_handler(c);
}
/* timer 1 */
else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
& BM_TIMROT_TIMCTRLn_IRQ) {
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
}
return IRQ_HANDLED;
}
static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
{
return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
& 0xFFFF0000) >> 16);
}
static int
stmp3xxx_timrot_set_next_event(unsigned long delta,
struct clock_event_device *dev)
{
/* reload the timer */
__raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
return 0;
}
static void
stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
struct clock_event_device *dev)
{
}
static struct clock_event_device ckevt_timrot = {
.name = "timrot",
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_next_event = stmp3xxx_timrot_set_next_event,
.set_mode = stmp3xxx_timrot_set_mode,
};
static struct clocksource cksrc_stmp3xxx = {
.name = "cksrc_stmp3xxx",
.rating = 250,
.read = stmp3xxx_clock_read,
.mask = CLOCKSOURCE_MASK(16),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static struct irqaction stmp3xxx_timer_irq = {
.name = "stmp3xxx_timer",
.flags = IRQF_DISABLED | IRQF_TIMER,
.handler = stmp3xxx_timer_interrupt,
.dev_id = &ckevt_timrot,
};
/*
* Set up timer interrupt, and return the current time in seconds.
*/
static void __init stmp3xxx_init_timer(void)
{
ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
ckevt_timrot.shift);
ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
ckevt_timrot.cpumask = cpumask_of(0);
stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
/* clear two timers */
__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
/* configure them */
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
__raw_writel(
(8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(CLOCK_TICK_RATE / HZ - 1,
REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
clockevents_register_device(&ckevt_timrot);
}
#ifdef CONFIG_PM
void stmp3xxx_suspend_timer(void)
{
stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
}
void stmp3xxx_resume_timer(void)
{
stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
__raw_writel(
8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
__raw_writel(
8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
BM_TIMROT_TIMCTRLn_RELOAD |
BM_TIMROT_TIMCTRLn_UPDATE |
BM_TIMROT_TIMCTRLn_IRQ_EN,
REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
__raw_writel(CLOCK_TICK_RATE / HZ - 1,
REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
}
#else
#define stmp3xxx_suspend_timer NULL
#define stmp3xxx_resume_timer NULL
#endif /* CONFIG_PM */
struct sys_timer stmp3xxx_timer = {
.init = stmp3xxx_init_timer,
.suspend = stmp3xxx_suspend_timer,
.resume = stmp3xxx_resume_timer,
};
arch/arm/plat-versatile/platsmp.c
View file @ 4b60e5f9
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#include <linux/smp.h> #include <linux/smp.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
/* /*
* control for which core is the next to come out of the secondary * control for which core is the next to come out of the secondary
...@@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
* the boot monitor to read the system wide flags register, * the boot monitor to read the system wide flags register,
* and branch to the address found there. * and branch to the address found there.
*/ */
smp_cross_call(cpumask_of(cpu), 1); gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ); timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
......
drivers/mtd/Kconfig
View file @ 4b60e5f9
...@@ -148,8 +148,7 @@ config MTD_AFS_PARTS ...@@ -148,8 +148,7 @@ config MTD_AFS_PARTS
You will still need the parsing functions to be called by the driver You will still need the parsing functions to be called by the driver
for your particular device. It won't happen automatically. The for your particular device. It won't happen automatically. The
'armflash' map driver (CONFIG_MTD_ARM_INTEGRATOR) does this, for 'physmap' map driver (CONFIG_MTD_PHYSMAP) does this, for example.
example.
config MTD_OF_PARTS config MTD_OF_PARTS
def_bool y def_bool y
......
drivers/mtd/maps/Makefile
View file @ 4b60e5f9
...@@ -8,7 +8,6 @@ endif ...@@ -8,7 +8,6 @@ endif
# Chip mappings # Chip mappings
obj-$(CONFIG_MTD_CDB89712) += cdb89712.o obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
obj-$(CONFIG_MTD_DC21285) += dc21285.o obj-$(CONFIG_MTD_DC21285) += dc21285.o
obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
......
drivers/mtd/maps/integrator-flash.c deleted 100644 → 0
View file @ e8765afe
/*======================================================================
drivers/mtd/maps/integrator-flash.c: ARM Integrator flash map driver
Copyright (C) 2000 ARM Limited
Copyright (C) 2003 Deep Blue Solutions Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
This is access code for flashes using ARM's flash partitioning
standards.
======================================================================*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/concat.h>
#include <asm/mach/flash.h>
#include <mach/hardware.h>
#include <asm/system.h>
struct armflash_subdev_info {
char *name;
struct mtd_info *mtd;
struct map_info map;
struct flash_platform_data *plat;
};
struct armflash_info {
struct resource *res;
struct mtd_partition *parts;
struct mtd_info *mtd;
int nr_subdev;
struct armflash_subdev_info subdev[0];
};
static void armflash_set_vpp(struct map_info *map, int on)
{
struct armflash_subdev_info *info =
container_of(map, struct armflash_subdev_info, map);
if (info->plat && info->plat->set_vpp)
info->plat->set_vpp(on);
}
static const char *probes[] = { "cmdlinepart", "RedBoot", "afs", NULL };
static int armflash_subdev_probe(struct armflash_subdev_info *subdev,
struct resource *res)
{
struct flash_platform_data *plat = subdev->plat;
resource_size_t size = res->end - res->start + 1;
void __iomem *base;
int err = 0;
if (!request_mem_region(res->start, size, subdev->name)) {
err = -EBUSY;
goto out;
}
base = ioremap(res->start, size);
if (!base) {
err = -ENOMEM;
goto no_mem;
}
/*
* look for CFI based flash parts fitted to this board
*/
subdev->map.size = size;
subdev->map.bankwidth = plat->width;
subdev->map.phys = res->start;
subdev->map.virt = base;
subdev->map.name = subdev->name;
subdev->map.set_vpp = armflash_set_vpp;
simple_map_init(&subdev->map);
/*
* Also, the CFI layer automatically works out what size
* of chips we have, and does the necessary identification
* for us automatically.
*/
subdev->mtd = do_map_probe(plat->map_name, &subdev->map);
if (!subdev->mtd) {
err = -ENXIO;
goto no_device;
}
subdev->mtd->owner = THIS_MODULE;
/* Successful? */
if (err == 0)
return err;
if (subdev->mtd)
map_destroy(subdev->mtd);
no_device:
iounmap(base);
no_mem:
release_mem_region(res->start, size);
out:
return err;
}
static void armflash_subdev_remove(struct armflash_subdev_info *subdev)
{
if (subdev->mtd)
map_destroy(subdev->mtd);
if (subdev->map.virt)
iounmap(subdev->map.virt);
kfree(subdev->name);
subdev->name = NULL;
release_mem_region(subdev->map.phys, subdev->map.size);
}
static int armflash_probe(struct platform_device *dev)
{
struct flash_platform_data *plat = dev->dev.platform_data;
unsigned int size;
struct armflash_info *info;
int i, nr, err;
/* Count the number of devices */
for (nr = 0; ; nr++)
if (!platform_get_resource(dev, IORESOURCE_MEM, nr))
break;
if (nr == 0) {
err = -ENODEV;
goto out;
}
size = sizeof(struct armflash_info) +
sizeof(struct armflash_subdev_info) * nr;
info = kzalloc(size, GFP_KERNEL);
if (!info) {
err = -ENOMEM;
goto out;
}
if (plat && plat->init) {
err = plat->init();
if (err)
goto no_resource;
}
for (i = 0; i < nr; i++) {
struct armflash_subdev_info *subdev = &info->subdev[i];
struct resource *res;
res = platform_get_resource(dev, IORESOURCE_MEM, i);
if (!res)
break;
if (nr == 1)
/* No MTD concatenation, just use the default name */
subdev->name = kstrdup(dev_name(&dev->dev), GFP_KERNEL);
else
subdev->name = kasprintf(GFP_KERNEL, "%s-%d",
dev_name(&dev->dev), i);
if (!subdev->name) {
err = -ENOMEM;
break;
}
subdev->plat = plat;
err = armflash_subdev_probe(subdev, res);
if (err) {
kfree(subdev->name);
subdev->name = NULL;
break;
}
}
info->nr_subdev = i;
if (err)
goto subdev_err;
if (info->nr_subdev == 1)
info->mtd = info->subdev[0].mtd;
else if (info->nr_subdev > 1) {
struct mtd_info *cdev[info->nr_subdev];
/*
* We detected multiple devices. Concatenate them together.
*/
for (i = 0; i < info->nr_subdev; i++)
cdev[i] = info->subdev[i].mtd;
info->mtd = mtd_concat_create(cdev, info->nr_subdev,
dev_name(&dev->dev));
if (info->mtd == NULL)
err = -ENXIO;
}
if (err < 0)
goto cleanup;
err = parse_mtd_partitions(info->mtd, probes, &info->parts, 0);
if (err > 0) {
err = add_mtd_partitions(info->mtd, info->parts, err);
if (err)
printk(KERN_ERR
"mtd partition registration failed: %d\n", err);
}
if (err == 0) {
platform_set_drvdata(dev, info);
return err;
}
/*
* We got an error, free all resources.
*/
cleanup:
if (info->mtd) {
del_mtd_partitions(info->mtd);
if (info->mtd != info->subdev[0].mtd)
mtd_concat_destroy(info->mtd);
}
kfree(info->parts);
subdev_err:
for (i = info->nr_subdev - 1; i >= 0; i--)
armflash_subdev_remove(&info->subdev[i]);
no_resource:
if (plat && plat->exit)
plat->exit();
kfree(info);
out:
return err;
}
static int armflash_remove(struct platform_device *dev)
{
struct armflash_info *info = platform_get_drvdata(dev);
struct flash_platform_data *plat = dev->dev.platform_data;
int i;
platform_set_drvdata(dev, NULL);
if (info) {
if (info->mtd) {
del_mtd_partitions(info->mtd);
if (info->mtd != info->subdev[0].mtd)
mtd_concat_destroy(info->mtd);
}
kfree(info->parts);
for (i = info->nr_subdev - 1; i >= 0; i--)
armflash_subdev_remove(&info->subdev[i]);
if (plat && plat->exit)
plat->exit();
kfree(info);
}
return 0;
}
static struct platform_driver armflash_driver = {
.probe = armflash_probe,
.remove = armflash_remove,
.driver = {
.name = "armflash",
.owner = THIS_MODULE,
},
};
static int __init armflash_init(void)
{
return platform_driver_register(&armflash_driver);
}
static void __exit armflash_exit(void)
{
platform_driver_unregister(&armflash_driver);
}
module_init(armflash_init);
module_exit(armflash_exit);
MODULE_AUTHOR("ARM Ltd");
MODULE_DESCRIPTION("ARM Integrator CFI map driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:armflash");
drivers/mtd/maps/physmap.c
View file @ 4b60e5f9
...@@ -67,9 +67,25 @@ static int physmap_flash_remove(struct platform_device *dev) ...@@ -67,9 +67,25 @@ static int physmap_flash_remove(struct platform_device *dev)
if (info->mtd[i] != NULL) if (info->mtd[i] != NULL)
map_destroy(info->mtd[i]); map_destroy(info->mtd[i]);
} }
if (physmap_data->exit)
physmap_data->exit(dev);
return 0; return 0;
} }
static void physmap_set_vpp(struct map_info *map, int state)
{
struct platform_device *pdev;
struct physmap_flash_data *physmap_data;
pdev = (struct platform_device *)map->map_priv_1;
physmap_data = pdev->dev.platform_data;
if (physmap_data->set_vpp)
physmap_data->set_vpp(pdev, state);
}
static const char *rom_probe_types[] = { static const char *rom_probe_types[] = {
"cfi_probe", "cfi_probe",
"jedec_probe", "jedec_probe",
...@@ -77,7 +93,8 @@ static const char *rom_probe_types[] = { ...@@ -77,7 +93,8 @@ static const char *rom_probe_types[] = {
"map_rom", "map_rom",
NULL }; NULL };
#ifdef CONFIG_MTD_PARTITIONS #ifdef CONFIG_MTD_PARTITIONS
static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "afs",
NULL };
#endif #endif
static int physmap_flash_probe(struct platform_device *dev) static int physmap_flash_probe(struct platform_device *dev)
...@@ -100,6 +117,12 @@ static int physmap_flash_probe(struct platform_device *dev) ...@@ -100,6 +117,12 @@ static int physmap_flash_probe(struct platform_device *dev)
goto err_out; goto err_out;
} }
if (physmap_data->init) {
err = physmap_data->init(dev);
if (err)
goto err_out;
}
platform_set_drvdata(dev, info); platform_set_drvdata(dev, info);
for (i = 0; i < dev->num_resources; i++) { for (i = 0; i < dev->num_resources; i++) {
...@@ -120,8 +143,9 @@ static int physmap_flash_probe(struct platform_device *dev) ...@@ -120,8 +143,9 @@ static int physmap_flash_probe(struct platform_device *dev)
info->map[i].phys = dev->resource[i].start; info->map[i].phys = dev->resource[i].start;
info->map[i].size = resource_size(&dev->resource[i]); info->map[i].size = resource_size(&dev->resource[i]);
info->map[i].bankwidth = physmap_data->width; info->map[i].bankwidth = physmap_data->width;
info->map[i].set_vpp = physmap_data->set_vpp; info->map[i].set_vpp = physmap_set_vpp;
info->map[i].pfow_base = physmap_data->pfow_base; info->map[i].pfow_base = physmap_data->pfow_base;
info->map[i].map_priv_1 = (unsigned long)dev;
info->map[i].virt = devm_ioremap(&dev->dev, info->map[i].phys, info->map[i].virt = devm_ioremap(&dev->dev, info->map[i].phys,
info->map[i].size); info->map[i].size);
......
drivers/mtd/maps/pismo.c
View file @ 4b60e5f9
...@@ -50,39 +50,13 @@ struct pismo_data { ...@@ -50,39 +50,13 @@ struct pismo_data {
struct platform_device *dev[PISMO_NUM_CS]; struct platform_device *dev[PISMO_NUM_CS];
}; };
/* FIXME: set_vpp could do with a better calling convention */ static void pismo_set_vpp(struct platform_device *pdev, int on)
static struct pismo_data *vpp_pismo;
static DEFINE_MUTEX(pismo_mutex);
static int pismo_setvpp_probe_fix(struct pismo_data *pismo)
{
mutex_lock(&pismo_mutex);
if (vpp_pismo) {
mutex_unlock(&pismo_mutex);
kfree(pismo);
return -EBUSY;
}
vpp_pismo = pismo;
mutex_unlock(&pismo_mutex);
return 0;
}
static void pismo_setvpp_remove_fix(struct pismo_data *pismo)
{
mutex_lock(&pismo_mutex);
if (vpp_pismo == pismo)
vpp_pismo = NULL;
mutex_unlock(&pismo_mutex);
}
static void pismo_set_vpp(struct map_info *map, int on)
{ {
struct pismo_data *pismo = vpp_pismo; struct i2c_client *client = to_i2c_client(pdev->dev.parent);
struct pismo_data *pismo = i2c_get_clientdata(client);
pismo->vpp(pismo->vpp_data, on); pismo->vpp(pismo->vpp_data, on);
} }
/* end of hack */
static unsigned int __devinit pismo_width_to_bytes(unsigned int width) static unsigned int __devinit pismo_width_to_bytes(unsigned int width)
{ {
...@@ -231,9 +205,6 @@ static int __devexit pismo_remove(struct i2c_client *client) ...@@ -231,9 +205,6 @@ static int __devexit pismo_remove(struct i2c_client *client)
for (i = 0; i < ARRAY_SIZE(pismo->dev); i++) for (i = 0; i < ARRAY_SIZE(pismo->dev); i++)
platform_device_unregister(pismo->dev[i]); platform_device_unregister(pismo->dev[i]);
/* FIXME: set_vpp needs saner arguments */
pismo_setvpp_remove_fix(pismo);
kfree(pismo); kfree(pismo);
return 0; return 0;
...@@ -257,11 +228,6 @@ static int __devinit pismo_probe(struct i2c_client *client, ...@@ -257,11 +228,6 @@ static int __devinit pismo_probe(struct i2c_client *client,
if (!pismo) if (!pismo)
return -ENOMEM; return -ENOMEM;
/* FIXME: set_vpp needs saner arguments */
ret = pismo_setvpp_probe_fix(pismo);
if (ret)
return ret;
pismo->client = client; pismo->client = client;
if (pdata) { if (pdata) {
pismo->vpp = pdata->set_vpp; pismo->vpp = pdata->set_vpp;
......
include/linux/mtd/physmap.h
View file @ 4b60e5f9
...@@ -22,7 +22,9 @@ struct map_info; ...@@ -22,7 +22,9 @@ struct map_info;
struct physmap_flash_data { struct physmap_flash_data {
unsigned int width; unsigned int width;
void (*set_vpp)(struct map_info *, int); int (*init)(struct platform_device *);
void (*exit)(struct platform_device *);
void (*set_vpp)(struct platform_device *, int);
unsigned int nr_parts; unsigned int nr_parts;
unsigned int pfow_base; unsigned int pfow_base;
char *probe_type; char *probe_type;
......
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