Commit 4c8eb19c authored by Paul Walmsley's avatar Paul Walmsley

riscv: tlbflush: remove confusing comment on local_flush_tlb_all()

Remove a confusing comment on our local_flush_tlb_all()
implementation.  Per an internal discussion with Andrew, while it's
true that the fence.i is not necessary, it's not the case that an
sfence.vma implies a fence.i.  We also drop the section about
"flush[ing] the entire local TLB" to better align with the language in
section 4.2.1 "Supervisor Memory-Management Fence Instruction" of the
RISC-V Privileged Specification v20190608.

Fixes: c901e45a ("RISC-V: `sfence.vma` orderes the instruction cache")
Reported-by: default avatarAlan Kao <alankao@andestech.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Andrew Waterman <andrew@sifive.com>
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent 2993c9b0
...@@ -10,10 +10,6 @@ ...@@ -10,10 +10,6 @@
#include <linux/mm_types.h> #include <linux/mm_types.h>
#include <asm/smp.h> #include <asm/smp.h>
/*
* Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
* cache as well, so a 'fence.i' is not necessary.
*/
static inline void local_flush_tlb_all(void) static inline void local_flush_tlb_all(void)
{ {
__asm__ __volatile__ ("sfence.vma" : : : "memory"); __asm__ __volatile__ ("sfence.vma" : : : "memory");
......
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