Commit 4c9456df authored by Jeremy Linton's avatar Jeremy Linton Committed by Arnd Bergmann

arm64: dts: juno: Correct PCI IO window

The PCIe root complex on Juno translates the MMIO mapped
at 0x5f800000 to the PIO address range starting at 0
(which is common because PIO addresses are generally < 64k).
Correct the DT to reflect this.
Signed-off-by: default avatarJeremy Linton <jeremy.linton@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 6e631f6d
...@@ -393,7 +393,7 @@ pcie_ctlr: pcie-controller@40000000 { ...@@ -393,7 +393,7 @@ pcie_ctlr: pcie-controller@40000000 {
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
dma-coherent; dma-coherent;
ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>, ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
......
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