Commit 4cce9c6d authored by Robert Richter's avatar Robert Richter Committed by Dave Jiang

cxl: Fix use of phys_to_target_node() for x86

The CXL driver uses both functions phys_to_target_node() and
memory_add_physaddr_to_nid(). The x86 architecture relies on the
NUMA_KEEP_MEMINFO kernel option enabled for both functions to work
correct. Update Kconfig to make sure the option is always enabled for
the driver.
Suggested-by: default avatarDan Williams <dan.j.williams@intel.com>
Link: http://lore.kernel.org/r/65f8b191c0422_aa222941b@dwillia2-mobl3.amr.corp.intel.com.notmuchReviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Link: https://lore.kernel.org/r/20240424154756.2152614-1-rrichter@amd.comSigned-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 4afaed94
...@@ -6,6 +6,7 @@ menuconfig CXL_BUS ...@@ -6,6 +6,7 @@ menuconfig CXL_BUS
select FW_UPLOAD select FW_UPLOAD
select PCI_DOE select PCI_DOE
select FIRMWARE_TABLE select FIRMWARE_TABLE
select NUMA_KEEP_MEMINFO if (NUMA && X86)
help help
CXL is a bus that is electrically compatible with PCI Express, but CXL is a bus that is electrically compatible with PCI Express, but
layers three protocols on that signalling (CXL.io, CXL.cache, and layers three protocols on that signalling (CXL.io, CXL.cache, and
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment