Commit 4e15eda4 authored by Andrew Morton's avatar Andrew Morton Committed by Linus Torvalds

[PATCH] Altix update: various, mainly cleanups

From: Pat Gefre <pfg@sgi.com>

arch/ia64/sn/io/machvec/pci_bus_cvlink.c
    Changes for new pcireg_ interfaces
    pcibr reorg
    Some code cleanup/reorg

arch/ia64/sn/io/machvec/pci_dma.c
    IS_PCIA64() not needed

arch/ia64/sn/io/sn2/ml_iograph.c
    new pcireg_ interface

arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
    code reorg/clean up

arch/ia64/sn/io/sn2/pcibr/pcibr_config.c
    code reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c
    Fixed the interface to these functions - one call/data type

arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pciio.c
    removed unused functions

arch/ia64/sn/io/sn2/pic.c
    reorg/cleanup

arch/ia64/sn/kernel/irq.c
    IS_PIC_SOFT not needed
    mod for new pcireg_ interfaces

include/asm-ia64/sn/module.h
    nodes/geoid[] -> MAX_SLABS

include/asm-ia64/sn/pci/bridge.h
    IS_[X]BRIDGE not needed

include/asm-ia64/sn/pci/pci_bus_cvlink.h
    SET_PCIA64 and IS_PCIA64 not needed
    isa64, dma_buf_sync, xbow_buf_sync gone

include/asm-ia64/sn/pci/pcibr.h
    mostly cleanup
    some reorg mods

include/asm-ia64/sn/pci/pcibr_private.h
    some reorg code
    protos for new pcireg_ interfaces

include/asm-ia64/sn/pci/pciio.h
    cleanup

include/asm-ia64/sn/pci/pic.h
    cleanup

include/asm-ia64/sn/sn2/intr.h
    changed IA64_SN2_FIRST_DEVICE_VECTOR and IA64_SN2_LAST_DEVICE_VECTOR
parent 839401aa
This diff is collapsed.
...@@ -247,18 +247,6 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire ...@@ -247,18 +247,6 @@ sn_pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int dire
for (i = 0; i < nents; i++, sg++) { for (i = 0; i < nents; i++, sg++) {
phys_addr = __pa((unsigned long)page_address(sg->page) + sg->offset); phys_addr = __pa((unsigned long)page_address(sg->page) + sg->offset);
/*
* Handle the most common case: 64 bit cards. This
* call should always succeed.
*/
if (IS_PCIA64(hwdev)) {
sg->dma_address = pcibr_dmatrans_addr(vhdl, NULL, phys_addr,
sg->length,
PCIIO_DMA_DATA | PCIIO_DMA_A64);
sg->dma_length = sg->length;
continue;
}
/* /*
* Handle 32-63 bit cards via direct mapping * Handle 32-63 bit cards via direct mapping
*/ */
...@@ -385,13 +373,6 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) ...@@ -385,13 +373,6 @@ sn_pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
dma_addr = 0; dma_addr = 0;
phys_addr = __pa(ptr); phys_addr = __pa(ptr);
if (IS_PCIA64(hwdev)) {
/* This device supports 64 bit DMA addresses. */
dma_addr = pcibr_dmatrans_addr(vhdl, NULL, phys_addr, size,
PCIIO_DMA_DATA | PCIIO_DMA_A64);
return dma_addr;
}
/* /*
* Devices that support 32 bit to 63 bit DMA addresses get * Devices that support 32 bit to 63 bit DMA addresses get
* 32 bit DMA addresses. * 32 bit DMA addresses.
......
...@@ -584,10 +584,9 @@ io_init_node(cnodeid_t cnodeid) ...@@ -584,10 +584,9 @@ io_init_node(cnodeid_t cnodeid)
} else { } else {
void *bridge; void *bridge;
extern uint64_t pcireg_control_get(void *);
bridge = (void *)NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0); bridge = (void *)NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0);
npdap->basew_id = pcireg_control_get(bridge) & WIDGET_WIDGET_ID; npdap->basew_id = pcireg_bridge_control_get(bridge) & WIDGET_WIDGET_ID;
printk(" ****io_init_node: Unknown Widget Part Number 0x%x Widget ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv); printk(" ****io_init_node: Unknown Widget Part Number 0x%x Widget ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
return; return;
......
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...@@ -34,22 +34,21 @@ void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t); ...@@ -34,22 +34,21 @@ void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
* the 32bit word that contains the "offset" byte. * the 32bit word that contains the "offset" byte.
*/ */
cfg_p cfg_p
pcibr_func_config_addr(bridge_t *bridge, pciio_bus_t bus, pciio_slot_t slot, pcibr_func_config_addr(pcibr_soft_t soft, pciio_bus_t bus, pciio_slot_t slot,
pciio_function_t func, int offset) pciio_function_t func, int offset)
{ {
/* /*
* Type 1 config space * Type 1 config space
*/ */
if (bus > 0) { if (bus > 0) {
bridge->b_pci_cfg = ((bus << 16) | (slot << 11)); pcireg_type1_cntr_set(soft, ((bus << 16) | (slot << 11)));
return &bridge->b_type1_cfg.f[func].l[(offset)]; return (pcireg_type1_cfg_addr(soft, func, offset));
} }
/* /*
* Type 0 config space * Type 0 config space
*/ */
slot++; return (pcireg_type0_cfg_addr(soft, slot, func, offset));
return &bridge->b_type0_cfg_dev[slot].f[func].l[offset];
} }
/* /*
...@@ -58,59 +57,21 @@ pcibr_func_config_addr(bridge_t *bridge, pciio_bus_t bus, pciio_slot_t slot, ...@@ -58,59 +57,21 @@ pcibr_func_config_addr(bridge_t *bridge, pciio_bus_t bus, pciio_slot_t slot,
* 32bit word that contains the "offset" byte. * 32bit word that contains the "offset" byte.
*/ */
cfg_p cfg_p
pcibr_slot_config_addr(bridge_t *bridge, pciio_slot_t slot, int offset) pcibr_slot_config_addr(pcibr_soft_t soft, pciio_slot_t slot, int offset)
{ {
return pcibr_func_config_addr(bridge, 0, slot, 0, offset); return pcibr_func_config_addr(soft, 0, slot, 0, offset);
}
/*
* Return config space data for given slot / offset
*/
unsigned
pcibr_slot_config_get(bridge_t *bridge, pciio_slot_t slot, int offset)
{
cfg_p cfg_base;
cfg_base = pcibr_slot_config_addr(bridge, slot, 0);
return (do_pcibr_config_get(cfg_base, offset, sizeof(unsigned)));
}
/*
* Return config space data for given slot / func / offset
*/
unsigned
pcibr_func_config_get(bridge_t *bridge, pciio_slot_t slot,
pciio_function_t func, int offset)
{
cfg_p cfg_base;
cfg_base = pcibr_func_config_addr(bridge, 0, slot, func, 0);
return (do_pcibr_config_get(cfg_base, offset, sizeof(unsigned)));
}
/*
* Set config space data for given slot / offset
*/
void
pcibr_slot_config_set(bridge_t *bridge, pciio_slot_t slot,
int offset, unsigned val)
{
cfg_p cfg_base;
cfg_base = pcibr_slot_config_addr(bridge, slot, 0);
do_pcibr_config_set(cfg_base, offset, sizeof(unsigned), val);
} }
/* /*
* Set config space data for given slot / func / offset * Set config space data for given slot / func / offset
*/ */
void void
pcibr_func_config_set(bridge_t *bridge, pciio_slot_t slot, pcibr_func_config_set(pcibr_soft_t soft, pciio_slot_t slot,
pciio_function_t func, int offset, unsigned val) pciio_function_t func, int offset, unsigned val)
{ {
cfg_p cfg_base; cfg_p cfg_base;
cfg_base = pcibr_func_config_addr(bridge, 0, slot, func, 0); cfg_base = pcibr_func_config_addr(soft, 0, slot, func, 0);
do_pcibr_config_set(cfg_base, offset, sizeof(unsigned), val); do_pcibr_config_set(cfg_base, offset, sizeof(unsigned), val);
} }
...@@ -124,8 +85,6 @@ pcibr_config_addr(vertex_hdl_t conn, ...@@ -124,8 +85,6 @@ pcibr_config_addr(vertex_hdl_t conn,
pciio_bus_t pciio_bus; pciio_bus_t pciio_bus;
pciio_slot_t pciio_slot; pciio_slot_t pciio_slot;
pciio_function_t pciio_func; pciio_function_t pciio_func;
pcibr_soft_t pcibr_soft;
bridge_t *bridge;
cfg_p cfgbase = (cfg_p)0; cfg_p cfgbase = (cfg_p)0;
pciio_info_t pciio_info; pciio_info_t pciio_info;
...@@ -164,11 +123,7 @@ pcibr_config_addr(vertex_hdl_t conn, ...@@ -164,11 +123,7 @@ pcibr_config_addr(vertex_hdl_t conn,
pciio_func = PCI_TYPE1_FUNC(reg); pciio_func = PCI_TYPE1_FUNC(reg);
} }
pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast; cfgbase = pcibr_func_config_addr((pcibr_soft_t) pcibr_info->f_mfast,
bridge = pcibr_soft->bs_base;
cfgbase = pcibr_func_config_addr(bridge,
pciio_bus, pciio_slot, pciio_func, 0); pciio_bus, pciio_slot, pciio_func, 0);
return cfgbase; return cfgbase;
......
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...@@ -133,11 +133,7 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask) ...@@ -133,11 +133,7 @@ sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
return; return;
cpu = first_cpu(mask); cpu = first_cpu(mask);
if (IS_PIC_SOFT(intr->bi_soft) ) { sn_shub_redirect_intr(intr, cpu);
sn_shub_redirect_intr(intr, cpu);
} else {
return;
}
(void) set_irq_affinity_info(irq, cpu_physical_id(intr->bi_cpu), redir); (void) set_irq_affinity_info(irq, cpu_physical_id(intr->bi_cpu), redir);
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
} }
...@@ -262,7 +258,7 @@ sn_check_intr(int irq, pcibr_intr_t intr) { ...@@ -262,7 +258,7 @@ sn_check_intr(int irq, pcibr_intr_t intr) {
unsigned long irr_reg; unsigned long irr_reg;
regval = pcireg_intr_status_get(intr->bi_soft->bs_base); regval = pcireg_intr_status_get(intr->bi_soft);
irr_reg_num = irq_to_vector(irq) / 64; irr_reg_num = irq_to_vector(irq) / 64;
irr_bit = irq_to_vector(irq) % 64; irr_bit = irq_to_vector(irq) % 64;
switch (irr_reg_num) { switch (irr_reg_num) {
......
...@@ -158,12 +158,9 @@ struct module_s { ...@@ -158,12 +158,9 @@ struct module_s {
spinlock_t lock; /* Lock for this structure */ spinlock_t lock; /* Lock for this structure */
/* List of nodes in this module */ /* List of nodes in this module */
cnodeid_t nodes[MODULE_MAX_NODES]; cnodeid_t nodes[MAX_SLABS + 1];
geoid_t geoid[MODULE_MAX_NODES]; geoid_t geoid[MAX_SLABS + 1];
struct {
char moduleid[8];
} io[MODULE_MAX_NODES];
int nodecnt; /* Number of nodes in array */
/* Fields for Module System Controller */ /* Fields for Module System Controller */
int mesgpend; /* Message pending */ int mesgpend; /* Message pending */
int shutdown; /* Shutdown in progress */ int shutdown; /* Shutdown in progress */
......
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