Commit 4e15f6d7 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Greg Kroah-Hartman

PCI: dwc: Remove default MSI initialization for platform specific MSI chips

[ Upstream commit fd8a44bd ]

Platforms which populate msi_host_init() have their own MSI controller
logic. Writing to MSI control registers on platforms which do not use
Designware's MSI controller logic might have side effects.

To be safe, do not write to MSI control registers if the platform uses
its own MSI controller logic instead of Designware's MSI one.
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 21bd6db4
...@@ -653,17 +653,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) ...@@ -653,17 +653,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_setup(pci); dw_pcie_setup(pci);
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; if (!pp->ops->msi_host_init) {
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
/* Initialize IRQ Status array */
for (ctrl = 0; ctrl < num_ctrls; ctrl++) { /* Initialize IRQ Status array */
pp->irq_mask[ctrl] = ~0; for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + pp->irq_mask[ctrl] = ~0;
(ctrl * MSI_REG_CTRL_BLOCK_SIZE), dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
4, pp->irq_mask[ctrl]); (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + 4, pp->irq_mask[ctrl]);
(ctrl * MSI_REG_CTRL_BLOCK_SIZE), dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
4, ~0); (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
4, ~0);
}
} }
/* Setup RC BARs */ /* Setup RC BARs */
......
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