Commit 4e3ecc28 authored by Zhang Rui's avatar Zhang Rui Committed by Rafael J. Wysocki

thermal/intel/intel_tcc_cooling: Use Intel TCC library

Cleanup the code by using Intel TCC library for TCC (Thermal Control
Circuitry) MSR access.
Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 955fb871
...@@ -88,6 +88,7 @@ config INTEL_PCH_THERMAL ...@@ -88,6 +88,7 @@ config INTEL_PCH_THERMAL
config INTEL_TCC_COOLING config INTEL_TCC_COOLING
tristate "Intel TCC offset cooling Driver" tristate "Intel TCC offset cooling Driver"
depends on X86 depends on X86
select INTEL_TCC
help help
Enable this to support system cooling by adjusting the effective TCC Enable this to support system cooling by adjusting the effective TCC
activation temperature via the TCC Offset register, which is widely activation temperature via the TCC Offset register, which is widely
......
...@@ -7,12 +7,11 @@ ...@@ -7,12 +7,11 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/device.h> #include <linux/device.h>
#include <linux/intel_tcc.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/thermal.h> #include <linux/thermal.h>
#include <asm/cpu_device_id.h> #include <asm/cpu_device_id.h>
#define TCC_SHIFT 24
#define TCC_MASK (0x3fULL<<24)
#define TCC_PROGRAMMABLE BIT(30) #define TCC_PROGRAMMABLE BIT(30)
#define TCC_LOCKED BIT(31) #define TCC_LOCKED BIT(31)
...@@ -21,47 +20,26 @@ static struct thermal_cooling_device *tcc_cdev; ...@@ -21,47 +20,26 @@ static struct thermal_cooling_device *tcc_cdev;
static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long
*state) *state)
{ {
*state = TCC_MASK >> TCC_SHIFT; *state = 0x3f;
return 0;
}
static int tcc_offset_update(int tcc)
{
u64 val;
int err;
err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val);
if (err)
return err;
val &= ~TCC_MASK;
val |= tcc << TCC_SHIFT;
err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val);
if (err)
return err;
return 0; return 0;
} }
static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long
*state) *state)
{ {
u64 val; int offset = intel_tcc_get_offset(-1);
int err;
err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); if (offset < 0)
if (err) return offset;
return err;
*state = (val & TCC_MASK) >> TCC_SHIFT; *state = offset;
return 0; return 0;
} }
static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long
state) state)
{ {
return tcc_offset_update(state); return intel_tcc_set_offset(-1, (int)state);
} }
static const struct thermal_cooling_device_ops tcc_cooling_ops = { static const struct thermal_cooling_device_ops tcc_cooling_ops = {
...@@ -140,6 +118,7 @@ static void __exit tcc_cooling_exit(void) ...@@ -140,6 +118,7 @@ static void __exit tcc_cooling_exit(void)
module_exit(tcc_cooling_exit) module_exit(tcc_cooling_exit)
MODULE_IMPORT_NS(INTEL_TCC);
MODULE_DESCRIPTION("TCC offset cooling device Driver"); MODULE_DESCRIPTION("TCC offset cooling device Driver");
MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>"); MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
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