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Kirill Smelkov
linux
Commits
4e484e7d
Commit
4e484e7d
authored
Jun 16, 2009
by
Michel Dänzer
Committed by
Dave Airlie
Jun 19, 2009
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Plain Diff
radeon: Fix CP byte order on big endian architectures with KMS.
Signed-off-by:
Dave Airlie
<
airlied@redhat.com
>
parent
62369028
Changes
2
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+4
-0
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r100.c
+3
-0
drivers/gpu/drm/radeon/radeon_reg.h
drivers/gpu/drm/radeon/radeon_reg.h
+1
-0
No files found.
drivers/gpu/drm/radeon/r100.c
View file @
4e484e7d
...
...
@@ -551,6 +551,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
/* cp setup */
WREG32
(
0x718
,
pre_write_timer
|
(
pre_write_limit
<<
28
));
WREG32
(
RADEON_CP_RB_CNTL
,
#ifdef __BIG_ENDIAN
RADEON_BUF_SWAP_32BIT
|
#endif
REG_SET
(
RADEON_RB_BUFSZ
,
rb_bufsz
)
|
REG_SET
(
RADEON_RB_BLKSZ
,
rb_blksz
)
|
REG_SET
(
RADEON_MAX_FETCH
,
max_fetch
)
|
...
...
drivers/gpu/drm/radeon/radeon_reg.h
View file @
4e484e7d
...
...
@@ -3184,6 +3184,7 @@
# define RADEON_RB_BUFSZ_MASK (0x3f << 0)
# define RADEON_RB_BLKSZ_SHIFT 8
# define RADEON_RB_BLKSZ_MASK (0x3f << 8)
# define RADEON_BUF_SWAP_32BIT (1 << 17)
# define RADEON_MAX_FETCH_SHIFT 18
# define RADEON_MAX_FETCH_MASK (0x3 << 18)
# define RADEON_RB_NO_UPDATE (1 << 27)
...
...
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