irqchip/meson-gpio: add support for Meson8 SoCs

Meson8 uses the same GPIO interrupt controller IP block as the other
Meson SoCs. A total of 134 pins can be spied on, which is the sum of:
- 22 pins on bank GPIOX
- 17 pins on bank GPIOY
- 30 pins on bank GPIODV
- 10 pins on bank GPIOH
- 15 pins on bank GPIOZ
- 7 pins on bank CARD
- 19 pins on bank BOOT
- 14 pins in the AO domain
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

@@ -10,6 +10,7 @@ number of interrupt exposed depends on the SoC.
 Required properties:
 
 - compatible : must have "amlogic,meson8-gpio-intc” and either
+   “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
    “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
    “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
    “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)

drivers/irqchip/irq-meson-gpio.c

@@ -47,6 +47,10 @@ struct meson_gpio_irq_params {
 	unsigned int nr_hwirq;
 };
 
+static const struct meson_gpio_irq_params meson8_params = {
+	.nr_hwirq = 134,
+};
+
 static const struct meson_gpio_irq_params meson8b_params = {
 	.nr_hwirq = 119,
 };
@@ -60,6 +64,7 @@ static const struct meson_gpio_irq_params gxl_params = {
 };
 
 static const struct of_device_id meson_irq_gpio_matches[] = {
+	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },