Commit 4ea5081c authored by Wenhui Sheng's avatar Wenhui Sheng Committed by Alex Deucher

drm/amd/powerplay: enable SMC message filter

1. enable SMC message filter in SRIOV situation
2. return -EACCESS if msg is blocked from smu_msg_get_index
3. if msg is block, always return 0 from smu_v11_0_send_msg_with_param
Signed-off-by: default avatarWenhui Sheng <Wenhui.Sheng@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d4f3c0b3
......@@ -208,6 +208,9 @@ static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
if (!(mapping.valid_mapping))
return -EINVAL;
if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
return -EACCES;
return mapping.map_to;
}
......@@ -382,11 +385,6 @@ arcturus_set_single_dpm_table(struct smu_context *smu,
return ret;
}
if (!num_of_levels) {
pr_err("[%s] number of clk levels is invalid!\n", __func__);
return -EINVAL;
}
single_dpm_table->count = num_of_levels;
for (i = 0; i < num_of_levels; i++) {
ret = smu_send_smc_msg_with_param(smu,
......@@ -397,10 +395,6 @@ arcturus_set_single_dpm_table(struct smu_context *smu,
pr_err("[%s] failed to get dpm freq by index!\n", __func__);
return ret;
}
if (!clk) {
pr_err("[%s] clk value is invalid!\n", __func__);
return -EINVAL;
}
single_dpm_table->dpm_levels[i].value = clk;
single_dpm_table->dpm_levels[i].enabled = true;
}
......
......@@ -228,6 +228,9 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
return -EINVAL;
}
if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
return -EACCES;
return mapping.map_to;
}
......
......@@ -100,7 +100,7 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu,
index = smu_msg_get_index(smu, msg);
if (index < 0)
return index;
return index == -EACCES ? 0 : index;
mutex_lock(&smu->message_lock);
ret = smu_v11_0_wait_for_response(smu);
......
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