Commit 4feffead authored by Rafał Miłecki's avatar Rafał Miłecki Committed by David S. Miller

net: broadcom: bcm4908enet: add BCM4908 controller driver

BCM4908 SoCs family uses Ethernel controller that includes UniMAC but
uses different DMA engine (than other controllers) and requires
different programming.
Signed-off-by: default avatarRafał Miłecki <rafal@milecki.pl>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 387d1c18
...@@ -3445,6 +3445,15 @@ F: Documentation/devicetree/bindings/mips/brcm/ ...@@ -3445,6 +3445,15 @@ F: Documentation/devicetree/bindings/mips/brcm/
F: arch/mips/bcm47xx/* F: arch/mips/bcm47xx/*
F: arch/mips/include/asm/mach-bcm47xx/* F: arch/mips/include/asm/mach-bcm47xx/*
BROADCOM BCM4908 ETHERNET DRIVER
M: Rafał Miłecki <rafal@milecki.pl>
M: bcm-kernel-feedback-list@broadcom.com
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml
F: drivers/net/ethernet/broadcom/bcm4908enet.*
F: drivers/net/ethernet/broadcom/unimac.h
BROADCOM BCM5301X ARM ARCHITECTURE BROADCOM BCM5301X ARM ARCHITECTURE
M: Hauke Mehrtens <hauke@hauke-m.de> M: Hauke Mehrtens <hauke@hauke-m.de>
M: Rafał Miłecki <zajec5@gmail.com> M: Rafał Miłecki <zajec5@gmail.com>
......
...@@ -51,6 +51,14 @@ config B44_PCI ...@@ -51,6 +51,14 @@ config B44_PCI
depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT
default y default y
config BCM4908ENET
tristate "Broadcom BCM4908 internal mac support"
depends on ARCH_BCM4908 || COMPILE_TEST
default y
help
This driver supports Ethernet controller integrated into Broadcom
BCM4908 family SoCs.
config BCM63XX_ENET config BCM63XX_ENET
tristate "Broadcom 63xx internal mac support" tristate "Broadcom 63xx internal mac support"
depends on BCM63XX depends on BCM63XX
......
...@@ -4,6 +4,7 @@ ...@@ -4,6 +4,7 @@
# #
obj-$(CONFIG_B44) += b44.o obj-$(CONFIG_B44) += b44.o
obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o
obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o
obj-$(CONFIG_BCMGENET) += genet/ obj-$(CONFIG_BCMGENET) += genet/
obj-$(CONFIG_BNX2) += bnx2.o obj-$(CONFIG_BNX2) += bnx2.o
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __BCM4908ENET_H
#define __BCM4908ENET_H
#define ENET_CONTROL 0x000
#define ENET_MIB_CTRL 0x004
#define ENET_MIB_CTRL_CLR_MIB 0x00000001
#define ENET_RX_ERR_MASK 0x008
#define ENET_MIB_MAX_PKT_SIZE 0x00C
#define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
#define ENET_DIAG_OUT 0x01c
#define ENET_ENABLE_DROP_PKT 0x020
#define ENET_IRQ_ENABLE 0x024
#define ENET_IRQ_ENABLE_OVFL 0x00000001
#define ENET_GMAC_STATUS 0x028
#define ENET_GMAC_STATUS_ETH_SPEED_MASK 0x00000003
#define ENET_GMAC_STATUS_ETH_SPEED_10 0x00000000
#define ENET_GMAC_STATUS_ETH_SPEED_100 0x00000001
#define ENET_GMAC_STATUS_ETH_SPEED_1000 0x00000002
#define ENET_GMAC_STATUS_HD 0x00000004
#define ENET_GMAC_STATUS_AUTO_CFG_EN 0x00000008
#define ENET_GMAC_STATUS_LINK_UP 0x00000010
#define ENET_IRQ_STATUS 0x02c
#define ENET_IRQ_STATUS_OVFL 0x00000001
#define ENET_OVERFLOW_COUNTER 0x030
#define ENET_FLUSH 0x034
#define ENET_FLUSH_RXFIFO_FLUSH 0x00000001
#define ENET_FLUSH_TXFIFO_FLUSH 0x00000002
#define ENET_RSV_SELECT 0x038
#define ENET_BP_FORCE 0x03c
#define ENET_BP_FORCE_FORCE 0x00000001
#define ENET_DMA_RX_OK_TO_SEND_COUNT 0x040
#define ENET_DMA_RX_OK_TO_SEND_COUNT_VAL 0x0000000f
#define ENET_TX_CRC_CTRL 0x044
#define ENET_MIB 0x200
#define ENET_UNIMAC 0x400
#define ENET_DMA 0x800
#define ENET_DMA_CONTROLLER_CFG 0x800
#define ENET_DMA_CTRL_CFG_MASTER_EN 0x00000001
#define ENET_DMA_CTRL_CFG_FLOWC_CH1_EN 0x00000002
#define ENET_DMA_CTRL_CFG_FLOWC_CH3_EN 0x00000004
#define ENET_DMA_FLOWCTL_CH1_THRESH_LO 0x804
#define ENET_DMA_FLOWCTL_CH1_THRESH_HI 0x808
#define ENET_DMA_FLOWCTL_CH1_ALLOC 0x80c
#define ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE 0x80000000
#define ENET_DMA_FLOWCTL_CH3_THRESH_LO 0x810
#define ENET_DMA_FLOWCTL_CH3_THRESH_HI 0x814
#define ENET_DMA_FLOWCTL_CH3_ALLOC 0x818
#define ENET_DMA_FLOWCTL_CH5_THRESH_LO 0x81C
#define ENET_DMA_FLOWCTL_CH5_THRESH_HI 0x820
#define ENET_DMA_FLOWCTL_CH5_ALLOC 0x824
#define ENET_DMA_FLOWCTL_CH7_THRESH_LO 0x828
#define ENET_DMA_FLOWCTL_CH7_THRESH_HI 0x82C
#define ENET_DMA_FLOWCTL_CH7_ALLOC 0x830
#define ENET_DMA_CTRL_CHANNEL_RESET 0x834
#define ENET_DMA_CTRL_CHANNEL_DEBUG 0x838
#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS 0x840
#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK 0x844
#define ENET_DMA_CH0_CFG 0xa00 /* RX */
#define ENET_DMA_CH1_CFG 0xa10 /* TX */
#define ENET_DMA_CH0_STATE_RAM 0xc00 /* RX */
#define ENET_DMA_CH1_STATE_RAM 0xc10 /* TX */
#define ENET_DMA_CH_CFG 0x00 /* assorted configuration */
#define ENET_DMA_CH_CFG_ENABLE 0x00000001 /* set to enable channel */
#define ENET_DMA_CH_CFG_PKT_HALT 0x00000002 /* idle after an EOP flag is detected */
#define ENET_DMA_CH_CFG_BURST_HALT 0x00000004 /* idle after finish current memory burst */
#define ENET_DMA_CH_CFG_INT_STAT 0x04 /* interrupts control and status */
#define ENET_DMA_CH_CFG_INT_MASK 0x08 /* interrupts mask */
#define ENET_DMA_CH_CFG_INT_BUFF_DONE 0x00000001 /* buffer done */
#define ENET_DMA_CH_CFG_INT_DONE 0x00000002 /* packet xfer complete */
#define ENET_DMA_CH_CFG_INT_NO_DESC 0x00000004 /* no valid descriptors */
#define ENET_DMA_CH_CFG_INT_RX_ERROR 0x00000008 /* rxdma detect client protocol error */
#define ENET_DMA_CH_CFG_MAX_BURST 0x0c /* max burst length permitted */
#define ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL 0x00040000 /* DMA Descriptor Size Selection */
#define ENET_DMA_CH_CFG_SIZE 0x10
#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR 0x00 /* descriptor ring start address */
#define ENET_DMA_CH_STATE_RAM_STATE_DATA 0x04 /* state/bytes done/ring offset */
#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS 0x08 /* buffer descriptor status and len */
#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR 0x0c /* buffer descrpitor current processing */
#define ENET_DMA_CH_STATE_RAM_SIZE 0x10
#define DMA_CTL_STATUS_APPEND_CRC 0x00000100
#define DMA_CTL_STATUS_APPEND_BRCM_TAG 0x00000200
#define DMA_CTL_STATUS_PRIO 0x00000C00 /* Prio for Tx */
#define DMA_CTL_STATUS_WRAP 0x00001000 /* */
#define DMA_CTL_STATUS_SOP 0x00002000 /* first buffer in packet */
#define DMA_CTL_STATUS_EOP 0x00004000 /* last buffer in packet */
#define DMA_CTL_STATUS_OWN 0x00008000 /* cleared by DMA, set by SW */
#define DMA_CTL_LEN_DESC_BUFLENGTH 0x0fff0000
#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT 16
#define DMA_CTL_LEN_DESC_MULTICAST 0x40000000
#define DMA_CTL_LEN_DESC_USEFPM 0x80000000
#endif
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