Commit 532abc3a authored by Naveen Krishna Ch's avatar Naveen Krishna Ch Committed by Sylwester Nawrocki

clk: samsung: add initial clock support for Exynos7 SoC

Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: default avatarNaveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: default avatarThomas Abraham <thomas.ab@samsung.com>
Tested-by: default avatarThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 0e5af270
* Samsung Exynos7 Clock Controller
Exynos7 clock controller has various blocks which are instantiated
independently from the device-tree. These clock controllers
generate and supply clocks to various hardware blocks within
the SoC.
Each clock is assigned an identifier and client nodes can use
this identifier to specify the clock which they consume. All
available clocks are defined as preprocessor macros in
dt-bindings/clock/exynos7-clk.h header and can be used in
device tree sources.
External clocks:
There are several clocks that are generated outside the SoC. It
is expected that they are defined using standard clock bindings
with following clock-output-names:
- "fin_pll" - PLL input clock from XXTI
Required Properties for Clock Controller:
- compatible: clock controllers will use one of the following
compatible strings to indicate the clock controller
functionality.
- "samsung,exynos7-clock-topc"
- "samsung,exynos7-clock-top0"
- "samsung,exynos7-clock-peric0"
- "samsung,exynos7-clock-peric1"
- "samsung,exynos7-clock-peris"
- reg: physical base address of the controller and the length of
memory mapped region.
- #clock-cells: should be 1.
- clocks: list of clock identifiers which are fed as the input to
the given clock controller. Please refer the next section to
find the input clocks for a given controller.
- clock-names: list of names of clocks which are fed as the input
to the given clock controller.
Input clocks for top0 clock controller:
- fin_pll
- dout_sclk_bus0_pll
- dout_sclk_bus1_pll
- dout_sclk_cc_pll
- dout_sclk_mfc_pll
Input clocks for peric0 clock controller:
- fin_pll
- dout_aclk_peric0_66
- sclk_uart0
Input clocks for peric1 clock controller:
- fin_pll
- dout_aclk_peric1_66
- sclk_uart1
- sclk_uart2
- sclk_uart3
Input clocks for peris clock controller:
- fin_pll
- dout_aclk_peris_66
...@@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o ...@@ -13,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
......
This diff is collapsed.
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
/* TOPC */
#define DOUT_ACLK_PERIS 1
#define DOUT_SCLK_BUS0_PLL 2
#define DOUT_SCLK_BUS1_PLL 3
#define DOUT_SCLK_CC_PLL 4
#define DOUT_SCLK_MFC_PLL 5
#define TOPC_NR_CLK 6
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
#define DOUT_ACLK_PERIC0 2
#define CLK_SCLK_UART0 3
#define CLK_SCLK_UART1 4
#define CLK_SCLK_UART2 5
#define CLK_SCLK_UART3 6
#define TOP0_NR_CLK 7
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
#define PERIC0_NR_CLK 3
/* PERIC1 */
#define PCLK_UART1 1
#define PCLK_UART2 2
#define PCLK_UART3 3
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
#define PERIC1_NR_CLK 7
/* PERIS */
#define PCLK_CHIPID 1
#define SCLK_CHIPID 2
#define PERIS_NR_CLK 3
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
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