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Commit 534e0ad2 authored by Yong Wu's avatar Yong Wu Committed by Krzysztof Kozlowski
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memory: mtk-smi: Adjust some code position 

No functional change. Only move the code position to make the code more
readable.
1. Put the register smi-common above smi-larb. Prepare to add some others
   register setting.
2. Put mtk_smi_larb_unbind around larb_bind.
3. Sort the SoC data alphabetically. and put them in one line as the
   current kernel allow it.
Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarIkjoon Jang <ikjn@chromium.org>
Link: https://lore.kernel.org/r/20210914113703.31466-6-yong.wu@mediatek.comSigned-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
parent a5c18986
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Showing with 75 additions and 113 deletions
drivers/memory/mtk-smi.c
View file @ 534e0ad2
...@@ -17,13 +17,16 @@ ...@@ -17,13 +17,16 @@
#include <dt-bindings/memory/mt2701-larb-port.h> #include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/memory/mtk-memory-port.h> #include <dt-bindings/memory/mtk-memory-port.h>
/* mt8173 */ /* SMI COMMON */
#define SMI_LARB_MMU_EN 0xf00 #define SMI_BUS_SEL 0x220
#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
/* All are MMU0 defaultly. Only specialize mmu1 here. */
#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
/* mt8167 */ /* SMI LARB */
#define MT8167_SMI_LARB_MMU_EN 0xfc0
/* mt2701 */ /* Below are about mmu enable registers, they are different in SoCs */
/* gen1: mt2701 */
#define REG_SMI_SECUR_CON_BASE 0x5c0 #define REG_SMI_SECUR_CON_BASE 0x5c0
/* every register control 8 port, register offset 0x4 */ /* every register control 8 port, register offset 0x4 */
...@@ -41,20 +44,21 @@ ...@@ -41,20 +44,21 @@
/* mt2701 domain should be set to 3 */ /* mt2701 domain should be set to 3 */
#define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
/* mt2712 */ /* gen2: */
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) /* mt8167 */
#define F_MMU_EN BIT(0) #define MT8167_SMI_LARB_MMU_EN 0xfc0
#define BANK_SEL(id) ({ \
/* mt8173 */
#define MT8173_SMI_LARB_MMU_EN 0xf00
/* general */
#define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
#define F_MMU_EN BIT(0)
#define BANK_SEL(id) ({ \
u32 _id = (id) & 0x3; \ u32 _id = (id) & 0x3; \
(_id << 8 | _id << 10 | _id << 12 | _id << 14); \ (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
}) })
/* SMI COMMON */
#define SMI_BUS_SEL 0x220
#define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
/* All are MMU0 defaultly. Only specialize mmu1 here. */
#define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
enum mtk_smi_type { enum mtk_smi_type {
MTK_SMI_GEN1, MTK_SMI_GEN1,
MTK_SMI_GEN2 MTK_SMI_GEN2
...@@ -140,36 +144,16 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) ...@@ -140,36 +144,16 @@ mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
return -ENODEV; return -ENODEV;
} }
static void mtk_smi_larb_config_port_gen2_general(struct device *dev) static void
{ mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
struct mtk_smi_larb *larb = dev_get_drvdata(dev);
u32 reg;
int i;
if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
return;
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
reg |= F_MMU_EN;
reg |= BANK_SEL(larb->bank[i]);
writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
}
}
static void mtk_smi_larb_config_port_mt8173(struct device *dev)
{ {
struct mtk_smi_larb *larb = dev_get_drvdata(dev); /* Do nothing as the iommu is always enabled. */
writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
} }
static void mtk_smi_larb_config_port_mt8167(struct device *dev) static const struct component_ops mtk_smi_larb_component_ops = {
{ .bind = mtk_smi_larb_bind,
struct mtk_smi_larb *larb = dev_get_drvdata(dev); .unbind = mtk_smi_larb_unbind,
};
writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
}
static void mtk_smi_larb_config_port_gen1(struct device *dev) static void mtk_smi_larb_config_port_gen1(struct device *dev)
{ {
...@@ -202,26 +186,36 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev) ...@@ -202,26 +186,36 @@ static void mtk_smi_larb_config_port_gen1(struct device *dev)
} }
} }
static void static void mtk_smi_larb_config_port_mt8167(struct device *dev)
mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
{ {
/* Do nothing as the iommu is always enabled. */ struct mtk_smi_larb *larb = dev_get_drvdata(dev);
writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
} }
static const struct component_ops mtk_smi_larb_component_ops = { static void mtk_smi_larb_config_port_mt8173(struct device *dev)
.bind = mtk_smi_larb_bind, {
.unbind = mtk_smi_larb_unbind, struct mtk_smi_larb *larb = dev_get_drvdata(dev);
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
/* mt8173 do not need the port in larb */ }
.config_port = mtk_smi_larb_config_port_mt8173,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
/* mt8167 do not need the port in larb */ {
.config_port = mtk_smi_larb_config_port_mt8167, struct mtk_smi_larb *larb = dev_get_drvdata(dev);
}; u32 reg;
int i;
if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
return;
for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
reg |= F_MMU_EN;
reg |= BANK_SEL(larb->bank[i]);
writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
}
}
static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
.port_in_larb = { .port_in_larb = {
...@@ -243,6 +237,16 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { ...@@ -243,6 +237,16 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
/* DUMMY | IPU0 | IPU1 | CCU | MDLA */ /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
}; };
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
/* mt8167 do not need the port in larb */
.config_port = mtk_smi_larb_config_port_mt8167,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
/* mt8173 do not need the port in larb */
.config_port = mtk_smi_larb_config_port_mt8173,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
.config_port = mtk_smi_larb_config_port_gen2_general, .config_port = mtk_smi_larb_config_port_gen2_general,
.larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
...@@ -254,34 +258,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { ...@@ -254,34 +258,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
}; };
static const struct of_device_id mtk_smi_larb_of_ids[] = { static const struct of_device_id mtk_smi_larb_of_ids[] = {
{ {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
.compatible = "mediatek,mt8167-smi-larb", {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
.data = &mtk_smi_larb_mt8167 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
}, {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
{ {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
.compatible = "mediatek,mt8173-smi-larb", {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
.data = &mtk_smi_larb_mt8173 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
},
{
.compatible = "mediatek,mt2701-smi-larb",
.data = &mtk_smi_larb_mt2701
},
{
.compatible = "mediatek,mt2712-smi-larb",
.data = &mtk_smi_larb_mt2712
},
{
.compatible = "mediatek,mt6779-smi-larb",
.data = &mtk_smi_larb_mt6779
},
{
.compatible = "mediatek,mt8183-smi-larb",
.data = &mtk_smi_larb_mt8183
},
{
.compatible = "mediatek,mt8192-smi-larb",
.data = &mtk_smi_larb_mt8192
},
{} {}
}; };
...@@ -438,34 +421,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { ...@@ -438,34 +421,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
}; };
static const struct of_device_id mtk_smi_common_of_ids[] = { static const struct of_device_id mtk_smi_common_of_ids[] = {
{ {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
.compatible = "mediatek,mt8173-smi-common", {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
.data = &mtk_smi_common_gen2, {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
}, {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
{ {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
.compatible = "mediatek,mt8167-smi-common", {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
.data = &mtk_smi_common_gen2, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
},
{
.compatible = "mediatek,mt2701-smi-common",
.data = &mtk_smi_common_gen1,
},
{
.compatible = "mediatek,mt2712-smi-common",
.data = &mtk_smi_common_gen2,
},
{
.compatible = "mediatek,mt6779-smi-common",
.data = &mtk_smi_common_mt6779,
},
{
.compatible = "mediatek,mt8183-smi-common",
.data = &mtk_smi_common_mt8183,
},
{
.compatible = "mediatek,mt8192-smi-common",
.data = &mtk_smi_common_mt8192,
},
{} {}
}; };
......
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