Commit 53bd5fed authored by Borislav Petkov's avatar Borislav Petkov

EDAC, AMD: decode FR MCEs

See Fam10h BKDG (31116, rev. 3.28), Table 101.
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent f9350efd
...@@ -321,6 +321,15 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) ...@@ -321,6 +321,15 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
} }
EXPORT_SYMBOL_GPL(amd_decode_nb_mce); EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
static void amd_decode_fr_mce(u64 mc5_status)
{
/* we have only one error signature so match all fields at once. */
if ((mc5_status & 0xffff) == 0x0f0f)
pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
else
pr_warning("Corrupted FR MCE info?\n");
}
static inline void amd_decode_err_code(unsigned int ec) static inline void amd_decode_err_code(unsigned int ec)
{ {
if (TLB_ERROR(ec)) { if (TLB_ERROR(ec)) {
...@@ -401,6 +410,10 @@ void decode_mce(struct mce *m) ...@@ -401,6 +410,10 @@ void decode_mce(struct mce *m)
amd_decode_nb_mce(node, &regs, 1); amd_decode_nb_mce(node, &regs, 1);
break; break;
case 5:
amd_decode_fr_mce(m->status);
break;
default: default:
break; break;
} }
......
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